Part Number:SN75DP139
Dear Sir,
Please you kindly help provide SN75DP139RGZR & SN75DP139RSBR Tj(max)..
I can't find on datasheet.
Thanks!
Steven
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SN75DP139: SN75DP139 TJ(max)
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USB-C-PD-DUO-EVM: TPS65987D registers I2C read back
Part Number:USB-C-PD-DUO-EVM
Dear Sir/Mam,
I'm trying to read back I2C registers from TPS65987D sink part of the USB-C-PD-DUO-EVM.
I get very strange values. Generally I read from addresses 0x38, 0x20, 0x21.
As far as I understand:
-slave address 0x38 represents I2C1, which is common for both sink and source ICs.
-slave address 0x20 represents I2C2, which is source IC.
-slave address 0x21 represents I2C2, which is sink IC.
I'm trying to read for example, register 3, and get "APP " from all 3 addresses, which is OK.
I'm trying to read register 4, and get "I2C " only from 0x38, the remaining 2 addresses return zeros.
When I'm trying to read Status, Power Path Status and Power Status registers, I get very unreasonable values.
What can be a reason for that?
Thanks a lot and Best Regards,
Boris.
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MSP432P401R: MSP432P401R
Part Number:MSP432P401R
Can you use the adc COMP_E module in an RTOS environment. I can run the COMP_E module using the driverlib example "comp_e_interrupt_output_toggle_vref12v", however, I cannot find a similar example under RTOS. I have tried running the driverlib code in an RTOS environment and while the program loads and runs there is no interrupt from P5.7. Can you point me in a direction to help me out.
thanks.
Dave
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CC1310: CC1310 Error Write to Internal Flash
Part Number:CC1310
Hi. I'm trying to write to internal flash a few bytes and trying to use function from this topic https://e2e.ti.com/support/wireless-connectivity/zigbee-and-thread/f/158/t/506551
But i have a problem when using flahread function with vims.c functions
voidFlashReadNonCache(uint8_t * pui8DataBuffer, uint32_t ui32Address, uint32_t ui32Count) { uint32_t OldVIMSState = VIMSModeGet(); VIMSModeSet(VIMS_BASE, VIMS_CTL_MODE_GPRAM); uint8_t* pui8ReadAddress = (uint8_t *)ui32Address; while(ui32Count--) { *Pui8DataBuffer++ = * pui8ReadAddress++; } VIMSModeSet(VIMS_BASE, OldVIMSState);}The error is:
error: too few arguments to function 'NOROM_VIMSModeGet'
uint32_t OldVIMSState = NOROM_VIMSModeGet();
../../arch/cpu/cc26x0-cc13x0/lib/cc13xxware/driverlib/vims.h:85:45: note: declared here
#define VIMSModeGet NOROM_VIMSModeGet
^
../../arch/cpu/cc26x0-cc13x0/lib/cc13xxware/driverlib/vims.h:226:17: note: in expansion of macro 'VIMSModeGet'
extern uint32_t VIMSModeGet(uint32_t ui32Base);
What i'm doing wrong?
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TMP20: TMP20 for Qualcomm platform.
Part Number:TMP20
Hi Expect:
Customer use TI TMP20 as Temperature sensor for our tablet projects on Qualcomm SDM450 platform.
Moreover, we use Qualcomm Sensor Core (SSC, it’s a sensor hub provided by Qualcomm) for all other sensors (A/M/Gyro/P/ALS), and would like to enable TMP20 for SSC.
Could you help to check if TMP20 could support Qualcomm SSC? If so, could you help provide the driver for it?
Best Regards,
Mark
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MUX509: Supply Current when Disabled
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TM4C1233H6PZ: USB interface lacks USB_VBUS signal
Part Number:TM4C1233H6PZ
The other microcontrollers in this family have a dedicated USB0VBUS pin, but this one does not. At least, the data sheet doesn’t show one. This one only has 2 USB signals, USB0M and USB0P.
I understand this signal is used as an input and an output when the USB enumerates. Two questions:
What hardware should I be using to interface the microcontroller to the VBUS pin on the USB connector?
What has to happen to the USB software driver to accommodate this?
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TM4C123GH6PM: TM4C123GH6PM:
Part Number:TM4C123GH6PM
i'm using tm4c123gh6pm kit , when i'm using a uart in kit i access something in wrong ,i was use my custom driver ,so the controller give me hw fault interrupt ,after many of tries the target goes to lock state and not accept any downloading however ICDI driver was known on device manager ,then i used LM flash to unlock ICDI but the operation dosen't success and the ICDI driver wasn't known by device manager ,when i connect the kit to my Lab-top no action occurs and no device driver for ICDI shown ,so i think that the ICDI Firmware goes lost and i need the bin file to flash it through jtag
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CCS/CC2640: BLE Stack support in GCC
Part Number:CC2640
Tool/software: Code Composer Studio
My customer looking to move from CCS to GCC and want to know if the BLE stack is supported in GCC.
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TIDEP0001: Confirm Schematic
Part Number:TIDEP0001
Hi,
Our customer want to verify the schematic diagram provided in TIDEP0001.
They noticed that U15 (MT41J128M16JT-125) in the schematic diagram of TIDEP0001 has pin "A14". However, when they checked the datasheet of the MT41J128M16JT-125 it has no "A14" pin.
TIDEP0001 Schematic Diagram: http://www.ti.com/lit/zip/tidr336
Regards,
Cedrick
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Compiler/TMS320C5535: TMS320C5535: msp430g2553: dlpc2607
Part Number:TMS320C5535
Tool/software: TI C/C++ Compiler
Hi,
I want to make a prototype for wearable glasses. Can anyone help me out regarding it?
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Basic 115VAC->3.3VDC power supply design questions
Hello Experts,
We'd like to build/procure? a power supply for a simple device we envision. Have done quite a bit of work on the embedded side, usually with pre-existing power solutions in place, but have never built a power supply ground up. Do we even need to? Frankly, I'd like some advice on how complicated this needs to be!
Upstream: power will be standard AC 'household' current; ideally the entire range from 115 through 230VAC.
The entire power load will be in the 3.3V MCU range. The circuit it will drive will be very low load; in fact, we'd like to avail ourselves of the MCU's low power mode, while keeping it responsive.
As the design will include one or more radio protocols - Bluetooth? TI 15.4?, I imagine the EMI noise factor will come into play.
Early research points to integrated monolithic transformer/regulator units, ready for solder, mostly non-TI. Would one of these be the way to go? I've begun to look at TI's Power Designer, but one can get in very deep very quickly here...
What are my next steps in terms of research - or can someone here point me to specific devices?
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ADS52J90: Bounds on t_PROP and delta-t_PROP parameters
Part Number:ADS52J90
The t_PROP and delta-t_PROP parameters are unbounded in the datasheet. Can you please provide information on the limits for these parameters? In particular, I want to determine if exceptional t_PROP values can cause sample-wise variance in latency between ADS52J90 devices in a multi-device system. If so, then the samples will not be aligned across multiple DAQ channels in the downstream DSP with respect to a common trigger signal. This trigger signal is not TX_TRIG.
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WL1837MOD: ETSI EN 301 893 V2.1.0 Annex G information
Part Number:WL1837MOD
Hi,
I'm creating a test plan for CE compliance and need to fill out Annex G form to book 5 GHz spurious tests, I found the Annex G info provided by TI but it's for an older version of the standard (V1.9.1), is there an updated version for V2.1.1?
Specifically there is a change at the end of the form, section r) With regards to Adaptivity for Load Based Equipment/ which i'm not sure how to answer.
https://www.etsi.org/deliver/etsi_en/301800_301899/301893/02.01.01_60/en_301893v020101p.pdf
Thanks,
Rowan
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IWR6843: Power consumption
Part Number:IWR6843
Hello team,
My customer encountered a new issue with a custom configuration with the IWR6843. Using 2TX, 4RX the board comes down, but with the same profile and only 3Rx antennas enabled, the board is fine. The customer suspects this is due to a power issue, and was wondering if there were more details on the IWR6843’s power consumption. The following is taken from p27 of the datasheet.
Thanks!
Errol
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XIO2213B: XIO2213BZAJ link between 1394 PHY and OCHI not setup
Part Number:XIO2213B
I am attempting to use the above device connected to a XILINX ZYNQ FPGA/Processor.
I have put this device on a CCA, and have tested the following:
- We can read the vendor ID using the PCIe interface in the ZYNQ.
- We can confirm that the PHY is running
- This is using a DAP Technologies 1394 PHYSPY.
It seems we are having an issue with getting the link between the PHY and OHCI link device is not setup.
Looking at the datasheet I can’t see any hardware pins that configure this.
Would anyone have any advice to provide me with?
Maybe something needs to be enabled in software, we can’t find a specific register in the datasheet to set to enable the PHY-OHCI link.
Reference design 7455.XIO2213ZAJ_REF was used for the hardware schematic capture.
XIO2213B implementation GUide scpa048 was used.
Also to add
The GPIO pins that are setup from the software are,
1394 PHY_RESET_N
1394 PHY_RESET_N_EN and
PERST
When the above GPIO pins are setup the topology appears in the Firespy as follows.
The “link layer active” should be yes for ID = 1 in the topology. That says that the link between the PHY and OCHI link device is not setup.
I am assuming the software or firmware don’t have any control over that setup.
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TINA/Spice/TPS2493: !PG pin and 9mS deglitch
Part Number:TPS2493
Tool/software:TINA-TI or Spice Models
Hi,
The TPS2493 datasheet describes the function of the PG open drain output pin. It states that the !PG pin will be open drain whenever the external FET Vds is > 2.7V, or UVEN is low or UVLO is active. It also then explains the 9mS deglitch timer. The block diagram of the IC shows that the 9mS deglitch is after the comparator which is monitoring Vds, whereas the UVLO and UVEN are inputs which control the enable of the fault logic circuit.
My question is this:
When I simulate the action of pulling low UVEN whilst the TPS2943 is active and the !PG pin is low (OUT has reached the VCC voltage), at the point at which UVEN goes low, !PG stays low for a further 9mS. Is this actually correct? The block diagram does not indicate entirely clearly how the !PG NFET is managed by the fault logic. The TINA model seems to indicate that the same 9mS de-glitch delay is also associated with changes detected at the UVEN pin and I assume also UVLO. The wording of the datasheet infers that all events that might cause !PG to go open drain are associated with the de-glitch circuit and regardless of the action which triggers !PG to go open drain there will always be 9mS of delay on the !PG pin. The TINA model reflects this inference.
Can you please clarify that this 9mS timer is seen with all events that cause !PG to go open drain.
Thanks
Aidan
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TLC5926: Clock width time
Part Number:TLC5926
Hello,
I'm using the TLC5926IPWPR in a design. The TLC5926IPWPR chip is on a separate PCB than the MCU that is controlling it. The Clock and SDO pin must go through a cable about a 1ft long. I want to clock this as fast as possible, and I wanted to get TI's opinion on my clock signal. The cable is affecting it quite a bit and I wanted to make sure I meet the minimum requirements, as this design will go into large quantitty production and I don't want 1 in 1000 units to loose a bit or something.
Also note that I have two of the TLC5926IPWPR cascaded.
Here is my clock without the cable from the MCU IO pin:
Here is my clock with the cable:
If I measure the time between the threshold of 0.7*Vdd and 0.3*Vdd, I get about 18nS. Is this the right way to measure the clock width requirement? It's the same time if I measure from 50% of Vdd as well.
Questions:
1) If the max clock is 30MHz, why is the min clock width 20ns? Shouldn't it be (1/30MHz)/2 = 16.67ns or less?
2) My clocks rise time is well under the maximum, but what about the clock width requirement of 20ns min? Is my clock sufficient?
3) Any ideas on how to clean this up so it matches the requirements better at 30MHz?
4) Does TI have a schmitt trigger or something that could clean the signal up from the MCU to meet the requirements?
The chips are working great and I don't see any issues, but one unit is hardly a valid test of that.
Thanks for any help.
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RTOS/LAUNCHXL-CC1352R1: Hwi_excHandler exception after some time
Part Number:LAUNCHXL-CC1352R1
Tool/software: TI-RTOS
Greetings,
I'm running a modified dmm_wsnnode_remote_display example on CC1352R1. The example is modified to send messages over Sub-1 GHz periodically. It's working fine but after a while it stuck in an exception in function "i_sysbios_family_arm_m3_Hwi_excHandler__I", which I can't find the implementation for.
It's the same issue that appeared in this thread but with different findings in CCS.
The exception details caught in "Clock" is:
"Caught exception in view init code: "C:/ti/xdctools_3_50_07_20_core/packages/xdc/rov/StructureDecoder.xs", line 518: java.lang.Exception: Target memory read failed at address: 0x200066c4, length: 32This read is at an INVALID address according to the application's section map. The application is likely either uninitialized or corrupt."
I tested many times, the exception happens after the same amount of time, in the same function and address, but the address of clock exception changes.
Could anyone support with this issue? and what can I check for it?
* James *
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CCS/CC2640R2F: When debug, always shows: Cortex_M3_0: Symbol Manager: the object file contains invalid call frame information at .debug_frame 0xafc9, the rest of call frame information will be skipped.
Part Number:CC2640R2F
Tool/software: Code Composer Studio
I'm using CCS V9 with customed BLE sensor device of CC264902F.
TI SimpleLink CC2640R2 Software Development Kit (Version 1.50.00.58)
TI Code Composer Studio: CCS-9
TI Code Generation Tools for ARM: 16.09.03.LTS
XDCTools: 3.50.03.3
Debugger: XDS110
BLE 4.2
When debug, it sometimes shows as below:
Cortex_M3_0: GEL Output: Memory Map Initialization Complete.
Cortex_M3_0: GEL Output: Board Reset Complete.
Cortex_M3_0: Symbol Manager: the object file contains invalid call frame information at .debug_frame 0xafc9; the rest of call frame information will be skipped. Callstack may not be unwound properly.
Is the yellow line an big error that will influence the debug result? Why it happened?
Thanks.
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