Part Number:CODECOMPOSER

Tool/software: Code Composer Studio

Using ccs version 8.3

Sdk: simplelink_msp432p4_sdk_2_40_00_10

Using: TIRTOS on MSP432P401R and MSP432P4111 Launchpads

Windows 10

I am trying to move an existing working project over to using sysconf. I assumed I could just use your file out of your example projects. The files are:

outofbox_msp432p401r.syscfg

outOfBox_msp432p4111.syscfg

I am attempting to get the Kentec Boosterpack touch screen to work with this code. My old code worked but this means sharing ADC pins with GPIO pins (for the touchscreen).

Before sysconf, I would just have the four needed GPIO lines defined as "Do not config". Unfortunately this does not work with sysconf as there is now a resource conflict with the ADC unit.

This should be allowed!

The GPIO pins I defined were "Dynamic" (aka Do not config). In my (working) code, the GPIO lines are used only outside any ADC_open / ADC_close calls, so this is a non-issue.

If anything, for a GPIO pin marked "Dynamic", the default conflicting pin error is ok, but an option to accept the conflict and allow it should be made available.

Sure I can “get around” this issue but it is not as clean as being able to put it in with sysconf.

Is there another way or am I missing something?

Another similar problem is when I added two ADC channels to the syscfg file and wanted to get ADCBuf support as well.

The ADCBuf reports an error but does not say what the error is – so I can’t fix it. It just has the red circle with an X beside the channel description:

> ADCBuf Channel 0(hide) <Insert red X here>

I am new to TI’s mcu offerings so I am not sure what this error is: is it another resource conflict or just a bug?

Well, enough issues for now. I’ll check back later on this post. (I need sleep.)

Part Number:LMR62014

Hi team,

The customer is using LMR62014 in the condition of 12Vin/15Vout as normal operation, but they observed that the output voltage is also gradually decreasing at <3.5Vin if the input voltage is gradually decreased as below.

12Vin --> 15Vout

10Vin --> 15Vout

5.0Vin --> 15Vout

3.3Vin --> 13.3Vout

3.0Vin --> 10.2Vout

2.7Vin --> 7.1Vout

The peripheral parameters are

- C1: 4.7uF

- L1: 10uH

- D1: MBR0520LT1G

- R1: 180kohm

- R2: 13.3k,ohm

- CF: 1000pF

- C2: 4.7uF

Could you tell us the reason the Vout is gradually decreasing at <3.5Vin along with the decrease of Vin?

Regards,

Jun 

Part Number:MSP430FR2633

Tool/software: Code Composer Studio

Hello,

in the CapTIvate Design Center it says that if the Conversion Count and Conversion Gain are set to the same value, the minimum amount of offset substraction is applied. In some other document I also read that no offset is applied at all (which does not seem to be true as far as I can tell). Now to my question: Does the "minimum offset amount" depend on the capacitance of the used electrode? I took various discrete capacitors and tried to measure/estimate (in mutual capacitance mode) their capacitances by enabling an internal reference capacitor (or by placing another external cap parallel to the first one) and compare the count to the LTA and any offset would distort the measurement. I assumed following formula for the measurement; with the capacitance of the external cap being the unknown variable:

C(external cap) x LTA = [C(external cap)+C(internal refcap)] x (LTA - Delta)

Up to 8.2 pF the caps could be measured kind of accurately if you keep the conversion count and gain below 250. Lower caps allowed higher count and gain values and some even required them. My larger caps (22 pF and 33 pF) on the other side were impossible to be measured accurately as the calculated values were way too low. I also made sure that there was (hopefully) enough time for the conversion by maxing out the charge and transfer phase lengths. At this point I assumed that there actually might be "large minimal offset subtraction". Maybe the captivate module does not work for these high capacitances and so it subtracts as less as possible (because of equal count and gain values) but as much as needed. Is this assumption true? To somehow verify this I lowered the conversion gain value and there were no changes in the delta and thus the sensitivity, which could mean it applied a large offset before, too, right? For my project the capacitances of my HID are in this range and I am also required to provide the absolute cap values during runtime. I am aware that the MSP430 is not specifically suited for this task, but its amount of channels and the CapTIvate module in general make it very comfortable to use. If I could also acquire information to which "known voltage" the external cap is charged and how large the internal sample capacitor is, I would probably benefit from it. 

Also I studied the automatically generated source code and couldn't find any function definitions for the calibration process or for any feature at all. The functions are all declared and I can use them, but I would also like to know how they work. The definitions have to be somewhere, right? Or are they precompiled and I am not even authorized to have access? Sorry if it is a dumb question or if I am too dumb to find what I'm looking for. I am not very experienced, yet. Thank you in advance!

Best regards,

Canbey

Part Number:DS90UB954-Q1

I'm currently testing the eye diagram of the CMLOUT of DS90UB960 deserializer. I'm using an SMA connector to connect the pins to the oscilloscope.

My question is: do i need to probe the reference clock of the deserializer for triggering?

What I previously did is to trigger only the positive (or negative) edge of the CMLOUT waveform, used infinite persistence, and measure the eye parameter of signal. I'd like to clarify if I also need to proce a reference clock to trigger on the reference clock edge. or does my initial procedure correct?

Part Number:AM5728

Tool/software: Linux

In the above thread, the solution has been provided for the EVM boards of AM5728, I was wondering if the same works for the Am5728 IDK board as well. I would like to access the GPIO, I2C, etc. of the IDK board

Part Number:CDCE62002

Hello,

I am using CDCE62002 as a jitter cleaner. So the external loop filter is used.

I can see the two cases of the VCO voltage.   Refer to the attached file.

/cfs-file/__key/communityserver-discussions-components-files/48/VCO-Lock-Voltage.pdf

- Even though the VCO voltage(EXT_LFN) is different, the output frequency of both cases is the same. (148.5MHz)   Why?

  (However Case 1 is better than Case2 for the jitter.)

- Is the VCO lock voltage affected by previous state?

-To lock the VCO voltage of Case1, do you have any solutions?

Best Regards,

Murai

Part Number:66AK2E05

Tool/software: TI C/C++ Compiler

Hi ,

I would like to setup own compilation environment  without ccs for being able to cross compile linux process binary for arm A15 cores . This should be done as part of automated building procedure

on Linux (CentOS 7) machine

Typically I would need the following (??)

SYSROOT,TOOLCHAIN

So question is if within keystone k2e sdk (ti-processor-sdk-linux-k2e-evm-05.00.00.15) these are the correct paths:

- linux-devkit/sysroots/x86_64-arago-linux/   or

- linux-devkit/sysroots/armv7ahf-neon-linux-gnueabi or none of these 2 ?

Then to "override" the host machine compilation tools/environment for example like this:

make CC="arm-linux-gnueabihf-gcc --sysroot=$SYSROOT -I=/usr/include -L=/usr/lib"

MOreover how can we setup as such for DSP core for TI-RTOS ?

Part Number:DS90UB954-Q1EVM

I have an LVDS Coaxial input (automotive) which needs to be converted to MIPI CSI2. Can I use DS90UB954-Q1EVM  to take the coax LVDS input and get MIPI CSI2 as output? Are there any limitations?

Part Number:LAUNCHXL-CC1310

Tool/software: TI-RTOS

HI,

I want to implement Wmbus in CC1310,

what is the lastest updates new on that from TI?

I have do little research on the forum , and come with some question whether to go with it

1)

is that the lastest release is of SWRA512.zip, and follow the dev note and modify the setting?

2)And i also find a software in link

so how should i start with it?

3)

and in this i find the max. no . of meter supported is 16?

is that right?

Thanks

Jeff

Part Number:CC3200

Hi experts,

This is the last time I'm asking this query so please sorry for that but here I'll explain my exact point what is the product and what is the requirement I want. So, first of all, We are making one product which is IOT based as you all are aware that anything data which is there on the Internet can be hackable if it is not secure. So we made one product and we want to add security in our third-party HTTP server so how can I make my own HTTP server as secure so it will not be hackable. How can I generate a certificate for that please tell me how to do it I shall be obliged for help.

Regards 

Manish

Part Number:DS90UB953-Q1

I've designed a 953 system, and I have a few clarifications regarding the POC trace:

the trace from DOUT+/- pins are designed 100R differential pairs up to the bypass capacitors. from the capacitors; the DOUT- trace is terminated to a 50R resistor while the DOUT+ trace is going to the connector.

the DOUT+ trace was designed to have 4.37mm total length and 0.4mm width. The recommended impedance of the single ended trace is 50R, but unfortunately, the design was calculated to have roughly 20R. Below points are the ideas behind the design:

• The system was initially designed to operate ~2W  at 4V input – that’s why the design increase the trace width.
• To satisfy the 50ohm impedance of the trace, it will be very narrow that the current capacity will suffer.
• The trace length is minimal enough to not compromise the stability of the link.

The Trace is intended to support 2G and 4G FPDIII Link. Can the design support the application? are the ideas behind the design valid?

Thanks in advance for the reply!

Part Number:AWR1443

Tool/software: Code Composer Studio

i'm trying to import a demo project from TI Resource Explorer but it fails and warning that some software(sys/bios and mmwave SDK) are not included, but i've got mmwave SDK on my computer, so how can i figure out this problem? should i move the sdk to a certain path?

Part Number:SN65LVDS4

Hi team,

    my customer take LMK05805 clock output (122.88MHz) as the SN65LVDS4 input, shown as below. In this way, the input is AC coupled and the voltage swing (VOH-VOL) is about 500~800mV. Could you please help to check whether only 100ohm differential resistance is ok? if external bias voltage is needed, whether following solution is ok? Thanks a lot!

Best Regards

Zhengquan Lu

Part Number:LM5146-Q1

Tool/software:TINA-TI or Spice Models

Hello!

I have been trying to run a simulation in TINA, but I am getting irregular circuit error message. The simulation I am trying to run is of LM5146-12VEVM. I used LM5146-Q1 PSpice model and connected all the components as per the EVM schematic. I rechecked the circuit and still getting an error. I have attached TINA file.What am I doing wrong??

Thanks

Nayana(Please visit the site to view this file)

Part Number:TPS3813

Is it OK to pull WDR, WDT up like this?

Part Number:MSP430FR5728

Tool/software: Code Composer Studio

hi

sir I am getting following error while running my code 

"../lnk_msp430fr5728.cmd", line 130: error #10099-D: program will not fit into available memory. placement with alignment fails for section "ALL_FRAM" size 0x4604 . Available memory ranges:
FRAM size: 0x3d80 unused: 0x3d80 max hole: 0x3d80

Sir please suggest me some solution for this problem.

Thanks

Part Number:TPS65251

Hi,

I am looking for Multi (Three) output Buck regulator with individual PGOOD & Enable pins for each output. The Input Voltage range is 4.5V to 15V and the Minimum output required is 0.8V. The Load current can be 1A/1A/1A. Can you suggest any part?

Regards,

Veerasamy

Part Number:ADS54J66EVM

Hi,

I'am using ADS54J66 evaluation board for JESD interface bring up using test patterns provided by the ADS54J66 ADC. link for the datasheet given below :

 http://www.ti.com/lit/ds/symlink/ads54j66.pdf.

I have made the setup by connecting the ADS54J66 eval board with  xilinx KC705 eval board and the ADC data is sent using JESD protocol using FMC connectors.

In KC705 eval board added JESD receiver core and AXI-stream FIFO and added stream signal to the chipscope and observed the data output on AXI-stream bus using chipscope below is the data observed on the AXI-stream bus of width 128.

In datasheet pg no 53 mentioned that different test patterns can be generated by the ADC chip.But not able to generate all mentioned test patterns mentioned in datasheet. Like

ADC page( 0Fh),register 74h.(7:4)

0000 = Normal operation using ADC output data - random data without adc input given.

0001 = Outputs all 0s  - Unable to generate.(00000000000000000000000000000000)

0010 = Outputs all 1s  - Unable to generate.(00000000000000000000000000000000)

0011 = Outputs toggle pattern: Output data are an alternating sequence of 101010101010 and 010101010101 - Able to generate(aaaa56555655aaaa5655aaaa5655aaaa)

0100 = Output digital ramp: output data increment by one LSB every clock cycle from code 0 to 16384 - Able to generate

0110 = Single pattern: output data are custom pattern 1 (75h and 76h)  - Unable to generate.(00000000000000000000000000000000)

0111 = Double pattern: output data alternate between custom pattern 1 and custom pattern 2 - Able to generate(but unable to generate when both the custom patterns are set to all zeros or all ones).

1000 = Deskew pattern: output data are 2AAAh - Able to generate (a8aea8aea8aea8aea8aea8aea8aea8ae)

1001 = SYNC pattern: output data are 3FFFh  - Unable to generate.(00000000000000000000000000000000)

can anyone explain the reason behind this peculiar observation.

Thanks in advance.

Part Number:TM4C1294NCPDT

Tool/software: TI-RTOS

Hello,

i have an TM4C1294NCPDT running TI-RTOS 2.16.1.14 on it. Code Composer Studio Version: 8.3.0.00009. Compiler 18.1.3.LTS. XDC 3.32.0.6.

On my board i have an powermonitor which gives me the temperature, voltage and current of my system, over an i2c bus. A task is polling the data in an endless loop with a Task_sleep(xxx) in it. There are like >10 Tasks running and my powermonitorTask has the lowest priority.

If the Task_sleep is 1ms it seems to work just fine, but if i increase the sleep time to 1s Task_sleep blocks after a certain amount of time. Why is that so?

I dont think the task is preemted because a different task with the same priority runs just fine and the idle task is able to reset my watchdog (which would cause a restart). When i change the Task_sleep to a Semaphore_pend(semHandle, 1000) which is never posted i get the same result (it runs ok for a certain amount of time and then blocks on semaphore_pend and never returns). When i change it to Semaphore_pend(semHandle, BIOS_WAIT_FOREVER) and post the semaphore in an timer it works with 1ms as wel as with 1s.

ROV shows me no errors.

void powermonitorTaskFxn(void)
{
    powerMonitorInitalized = false;

    while (1)
    {
        I2C_Params_init(&i2cParams);
        i2cParams.bitRate = I2C_400kHz;
        i2cParams.transferMode = I2C_MODE_BLOCKING;
        powerMonitor.alert = false;
        powerMonitorComstats.errorCounter = 0;

        printLog("trying to init powermonitor\n", INFOMSG, 1);

        while (!powerMonitorInitalized)
        {
            powerMonitorInitalized = initPowerMonitor();
            Task_sleep(100);
        }

        printLog("powermonitor init successfully!\n", INFOMSG, 1);

        while (powerMonitorInitalized)
        {
//            Semaphore_pend(powerMonitorSemaphoreHandle, 1000);

            printLog("reading temp!\n", INFOMSG, 20);
            readTemperature();
            Task_sleep(POWERMONITOR_WAIT_TIME);
            printLog("temp read!\n", INFOMSG, 20);

            printLog("reading voltage!\n", INFOMSG, 20);
            readVoltage();
            Task_sleep(POWERMONITOR_WAIT_TIME);
            printLog("voltage read!\n", INFOMSG, 20);

            printLog("reading current!\n", INFOMSG, 20);
            readCurrent();
            Task_sleep(POWERMONITOR_WAIT_TIME);
            printLog("current read!\n", INFOMSG, 20);

            printLog("reading power!\n", INFOMSG, 20);
            readPower();
            Task_sleep(POWERMONITOR_WAIT_TIME);
            printLog("power read!\n", INFOMSG, 20);

            printLog("reading status!\n", INFOMSG, 20);
            uint8_t status = readStatusRegister();
            setErrorFlags(status);
            printLog("status read!\n", INFOMSG, 20);

            Task_sleep(1000);
        }

        printLog("!powerMonitorInitalized\n", INFOMSG, 1);

        Task_sleep(10);
    }
}

What am i doing wrong? Why does Task_sleep never return?

Best Regards

Part Number:AM5728

Tool/software: TI-RTOS

I am using am57xx-evm board.  when I use MACHINE=am57xx-evm bitbake dspdce-fw is gives an error below.

ERROR: dspdce-fw-1.00.00.07-r4 do_compile: Function failed: do_compile (log file is located at /home/user/yocto/src_AM57XX/yocto_ti/build/arago-tmp-external-linaro-toolchain/work/armv7ahf-neon-linux-gnueabi/dspdce-fw/1.00.00.07-r4/temp/log.do_compile.10281)
ERROR: Logfile of failure stored in: /home/user/yocto/src_AM57XX/yocto_ti/build/arago-tmp-external-linaro-toolchain/work/armv7ahf-neon-linux-gnueabi/dspdce-fw/1.00.00.07-r4/temp/log.do_compile.10281
Log data follows:
| DEBUG: Executing shell function do_compile
| export XDCARGS="profile=release trace_level=0 hw_type=VAYU hw_version=ES10 BIOS_type=non-SMP"; \
| /home/user/yocto/src_AM57XX/yocto_ti/build/arago-tmp-external-linaro-toolchain/work/armv7ahf-neon-linux-gnueabi/dspdce-fw/1.00.00.07-r4/recipe-sysroot/usr/share/ti/ti-xdctools-tree/xdc --jobs=1 -PD /home/user/yocto/src_AM57XX/yocto_ti/build/arago-tmp-external-linaro-toolchain/work/armv7ahf-neon-linux-gnueabi/dspdce-fw/1.00.00.07-r4/git/platform/ti/dce/baseimage/.
| /bin/sh: line 1: /home/user/yocto/src_AM57XX/yocto_ti/build/arago-tmp-external-linaro-toolchain/work/armv7ahf-neon-linux-gnueabi/dspdce-fw/1.00.00.07-r4/recipe-sysroot/usr/share/ti/ti-xdctools-tree/xdc: No such file or directory
| Makefile:112: recipe for target 'build' failed
| make: *** [build] Error 127
| WARNING: /home/user/yocto/src_AM57XX/yocto_ti/build/arago-tmp-external-linaro-toolchain/work/armv7ahf-neon-linux-gnueabi/dspdce-fw/1.00.00.07-r4/temp/run.do_compile.10281:1 exit 2 from 'make dspbin'
| ERROR: Function failed: do_compile (log file is located at /home/user/yocto/src_AM57XX/yocto_ti/build/arago-tmp-external-linaro-toolchain/work/armv7ahf-neon-linux-gnueabi/dspdce-fw/1.00.00.07-r4/temp/log.do_compile.10281)
ERROR: Task (/home/user/yocto/src_AM57XX/yocto_ti/sources/meta-ti/recipes-bsp/dspdce-fw/dspdce-fw_git.bb:do_compile) failed with exit code '1'
NOTE: Tasks Summary: Attempted 804 tasks of which 796 didn't need to be rerun and 1 failed.

Summary: 1 task failed:
  /home/user/yocto/src_AM57XX/yocto_ti/sources/meta-ti/recipes-bsp/dspdce-fw/dspdce-fw_git.bb:do_compile
Summary: There were 8 WARNING messages shown.
Summary: There was 1 ERROR message shown, returning a non-zero exit code.