Hi,
Work for a company that does a lot of SDI. I have a 'good' well reviewed layout, and I am an rf guy myself. On my third revision of the PCB. Ten Layers, kept to guidelines in Revision C of spec. 2V5 Supply, SPI driven from 3V3 CPLD so voltage dividers as per the specification. Got caught out on the parasitic capacitance problem on loop filter (which seems still very touchy), pulled the ground from under pins and loop filter cap hoping would fix ... but still find some devices lose lock on (high quality) 3GHz SDI source.
I am waiting the recommended time before talking on the SPI.
Has anyone else had problems with this device?
I am continually polling the the status registers of the reclocker ... 1MHz SPI clock ... had a good look on a scope and the signals are ok, and timing looks fine. I have two reclockers on board ... one works one seems to occassionally lose lock. They are about 20cms apart, driven from independant SPI buses except clock.
Wondering if low frequency SPI could be injecting noise into and reducing margins in the loop filter. Will experiment with higher clock frequencies - but got to the point where invested to much effort trying to get this national/T.I device working.
Its close to being kicked to the curb unfortunately!
Any Ideas or experience with this device appreciated.
Thanks in advance!