Part Number:66AK2L06
Hello Yordan, just wanted to post to say thanks. We now have the 66AK2L06 EVM with our AD9250 (ADC) and the AD9152(DAC) now talking over the JESD interface, which implies
all of the lane assignments called out below are correct for the EVM/daughter connections. Our daughter board was designed soley to test the JESD interface to the analog devices parts
which we will be using in a small form factored radar along with the Texas Instruments 66AK2L06 device.
On another note, since I have this open, the one last thing we are still struggling with is getting our own code compiled into the NAND flash which will be our boot device. We can program the flash
but when we turn off the system and back on it is not booting? The software group is working on this, but as the hardware designer I am having a hard time understanding why this is such a hard thing
to do. Can you give me a step-by-step direction on how to compile our application (along with whatever else is needed) and store to NAND such than we can turn off the EVM and back on and it runs our application!
Our hardware JESD lane setup for our protoboard connected to the EVM:
For our DAC: (Using JESD subclass1, with 122.88MHZ CLOCK with 120KHZ sys ref as generated from EVM)
66AK2L06 transmit output [SHARED_SERDES_0] JESD channel 0 differential pins AH18/AH17 => ROUTE TO => FMC1 connector differential pins C2/C3
66AK2L06 transmit output [SHARED_SERDES_0] JESD channel 1 differential pins AG19/AG18 => ROUTE TO => FMC1 connector differential pins A22/A23
For our ADC: (Using JESD subclass 1, with 122.88MHZ CLOCK with 120KHZ sys ref as generated from EVM)
66AK2L06 receive input [SHARED_SERDES_0] JESD channel 0 differential pins AJ18/AJ19 <= ROUTE FROM <= FMC1 connector differential pins C6/C7
66AK2L06 receive input [SHARED_SERDES_0] JESD channel 1 differential pins AK19/AK20 <= ROUTE FROM <= FMC1 connector differential pins A2/A3
For the ADC sync:
66AK2L06 sync input [SOC_JESD_SYNCOUT0_P_FMC1 ] differential pins AJ9/AJ10 => ROUTE TO => FMC1 connector differential pins G12/G13
For the DAC sync:
66AK2L06 sync input [SOC_JESD_SYNCIN0_P ] differential pins AG12/AG13 <= ROUTE FROM <= U48 buffer pins 1/2 <= ROUTE FROM <= FMC1 connector differential pins F10/F11
For the ADC/DAC primary sampling clock: (Using the 122.88MHZ)
U47 CDCM6208V1RGZR [SYS_CLKP_FMC1 ] differential pins 23/22 => ROUTE TO => FMC1 connector differential pins K4/K5
For the ADC/DAC system reference strobe: (Using the 120KHZ generated from Xilinx fpga)
U51 SN65LVDS104PWR [SYSREF_P_FMC1] differential pins 14/13 => ROUTE TO => FMC1 connector differential pins J2/J3