Part Number:TMS320F28075
Tool/software: Code Composer Studio
Hi,
I am working on TMS320f28075 32 bit microcontroller for ZVS full bridge application.
I used two sets of PWMs (PWM2A, PWM2B and PWM6A, PWM6B )for generating phase shifted PWM. PWM2B and 6B are complimentary signals of PWM2A and 6A respectively. PWM2A and 6A corresponds to top switches and PWM2B and 6B for bottom switches.The Pulse width was set for 50% duty cycle using CMP registers. TBPHS register was used to phase shift the PWMs. I find that when the PWM is turned ON, the first pulse observed is less than 50% duty and is different for PWM2A and PWM6A.(see figure below).I tried turning on various times and each instance showed different behaviour. Note that this behaviour is observed only in first cycle of PWM. Could anyone tell me what could have gone wrong? Following is the configuration used for PWM module:
EPwm2Regs.TBPRD = 1200;
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; //High Speed Time Base Clock Pre-Scale Bits,TBCLK = EPWMCLK / (HSPCLKDIV x CLKDIV)., PWM period = 2 × TBPRD × TBCLK
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm2Regs.TBCTL.bit.FREE_SOFT = 2u;
EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE;
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
EPwm2Regs.CMPA.bit.CMPA = 300;
EPwm2Regs.CMPB.bit.CMPB = 300;
EPwm2Regs.AQCTLA.bit.CAU = AQ_SET;
EPwm2Regs.AQCTLA.bit.CBU = AQ_NO_ACTION;
EPwm2Regs.AQCTLA.bit.CBD = AQ_NO_ACTION;
EPwm2Regs.AQCTLA.bit.CAD = AQ_CLEAR;
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADASYNC=CC_CTR_ZERO;
EPwm2Regs.CMPCTL.bit.LOADAMODE=CC_CTR_ZERO;
EPwm2Regs.AQCTLB.bit.CAU = AQ_CLEAR;
EPwm2Regs.AQCTLB.bit.CBU = AQ_NO_ACTION;
EPwm2Regs.AQCTLB.bit.CBD = AQ_NO_ACTION;
EPwm2Regs.AQCTLB.bit.CAD = AQ_SET;
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADASYNC=CC_CTR_ZERO;
EPwm2Regs.CMPCTL.bit.LOADAMODE=CC_CTR_ZERO;
EPwm6Regs.TBPRD = PWM_TBPRD;
EPwm6Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;
EPwm6Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm6Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; //High Speed Time Base Clock Pre-Scale Bits,TBCLK = EPWMCLK / (HSPCLKDIV x CLKDIV)., PWM period = 2 × TBPRD × TBCLK
EPwm6Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm6Regs.TBCTL.bit.FREE_SOFT = 2u;
EPwm6Regs.TBCTL.bit.PHSEN = TB_ENABLE;
EPwm6Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
EPwm6Regs.CMPA.bit.CMPA = 300;
EPwm6Regs.CMPB.bit.CMPB = 300;
EPwm6Regs.AQCTLA.bit.CAD = AQ_CLEAR;
EPwm6Regs.AQCTLA.bit.CBD = AQ_NO_ACTION;
EPwm6Regs.AQCTLA.bit.CBU = AQ_NO_ACTION;
EPwm6Regs.AQCTLA.bit.CAU = AQ_SET;
EPwm6Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm6Regs.CMPCTL.bit.LOADASYNC=CC_CTR_ZERO;
EPwm6Regs.CMPCTL.bit.LOADAMODE=CC_CTR_PRD;
/* For OUtput B */
// Action Qualifier SubModule Registers
EPwm6Regs.AQCTLB.bit.CAU = AQ_CLEAR;
EPwm6Regs.AQCTLB.bit.CBU = AQ_NO_ACTION;
EPwm6Regs.AQCTLB.bit.CBD = AQ_NO_ACTION;
EPwm6Regs.AQCTLB.bit.CAD =AQ_SET;
EPwm6Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm6Regs.CMPCTL.bit.LOADASYNC=CC_CTR_ZERO;
EPwm6Regs.CMPCTL.bit.LOADAMODE=CC_CTR_PRD;
I am updating the TBPHS register of PWM 6 in CLA interrupt.
Figure: M is the difference between C1 and C3.
Thanks in advance!
Regards,
Anjana