Part Number:66ak2h14
Tool/software:TI-RTOS
Hello,
I have a 66ak2h14, running TI RTOS, running as a root complex, connected via PCIe to a Virtex-6.
I am running a modified variant of the PCIe example, which was written to transfer data between two eval cards. In our case, we write a PCIe buffer address to the Virtex, and it burst transfers about 1K of data to the PCIe memory address which we provided. We have modified the example so that it is root complex only.
All works well but I have questions about inbound mapping.
- We are using a similar setup to that used by the test program. We set BAR1 on the RC (TI) to 0x9000_0000. The BAR1 mask is still 0x00ff_ffff, as is used in the test software. We alter the inbound mapping so that 0x9000_0000 is mapped to our buffer address, in this case 0x8005_4700. This works fine.
- However, with that same setup, if we configure the Virtex to transfer data to address 0x8000_1000 instead of 0x9000_0000, then the data does indeed get deposited in memory at 0x8000_1000. From what I understand, this is not within the range of BAR1 on the root controller. I can also set up the Virtex to transfer to 0x8005_4700 (the real buffer address prior to inbound mapping), and the data is written into the real buffer. When I do this, the data is deposited within the real buffer. Note that these latter two addresses (0x8000_1000 and 0x8005_4700) are not within the range of BAR1, and the SOC accepts the transfers and writes the data into SDRAM without translating the address.
Chipscope in the FPGA verifies that the target addresses are 0x9000_0000, 0x8000_1000, and 0x8005_4700 for the three test cases, respectively.
My expectation was that since these addresses were outside the range of BAR1, that the transfers would not occur at all.
Note that MEMSPACE is all zeros, as it is in the PCIe example program.
BAR1 settings are 0x9000_0000, RC_MODE, non-prefetched, TYPE32, MEM.
Questions:
1) When a burst transfer occurs to an address that is outside the range of the BAR (0x8000_1000, for example), I would expect the RC to not accept the data, yet it transfers the data directly into SDRAM at that address, which is not altered by inbound translation. How do we restrict the address range of inbound transfers to the range defined by BAR1?
2) The documentation is not clear regarding what happens when the MEMSPACE register is all zeroes:
a) Does this mean translate everything, or nothing?
b) Are the memory limit and base addresses in MEMSPACE the "before" translation values?
c) Is the limit value inclusive? That is, if MEMSPACE is 0xa0008000, does this define a space from 0x8000_0000 through 0xAFFF_FFFF, or through 0x9FFF_FFFF?
Register values starting at 0x2180_1000: (xxxxxxxx = don't care/did not record)
21801000: xxxxxxxx xxxxxxxx xxxxxxxx 00010000
21801010: 00000000 90000000 00000000 00000000
21801020: 00000000 00000000 00000000 00000000
21801030: 00000000 00000040 00000000 000001ff
Thank you!
Tim