Dear TI,
We seem to observe a strange HW issue and I was wondering if someone could confirm.
When setting the bootstrap for the SPI, 2 bits are allocated to the chip select.
Here is what our HW engineer (using a scope to probe the pins straight from DSP) is reporting to me about this settings:
00=> CS0 active
01=> No CS active
10=> CS0 active
11 => No CS active
We have been trying to boot from SPI on CS1with no success. Can someone let us know if there is a problem in the RBL?
By the way, this test needs to be done without the IBL/FPGA of the EVM since the FPGA of the EVM samples the bootstrap, force a boot from I2C and then reconfigure the SPI module. The devstat informs that after this has occur, the values were 00.
I would be grateful for an answer.