Part Number:AFE5401-Q1
Hi,
One of the customers I support has following questions .
We use the AFE5401Q1 frontend chip.
Used datasheets: revision 2014 and rev 2017 AFE5401Q1
We have problems with the CLKINP/CLKINM input circuit:
- In datasheet: input is auto-detecting : DIFF or Single Ended
In datasheet: a register bit for selecting the CLKIN type (DIFF or Single Ended)(register 1, bit 2)
Q1: why is there a bit when auto-detection is available?
Q2: what does the register bit? Does the bit have priority over the auto-detection or the other way around?
Q3: we use Single Ended in our design, do we need to set this bit at “Single Ended” or is it a don’t care?
Q4: are there other bits that needs to be set for getting the right CLKIN settings?
All questions are asked because we see strange behavior at the DSYNC1/DCLK outputs. This depends on how the CLKINP is driven. This clock input drives several internal circuit. (ADC / DSYNC/D[0-11], GPIO, DCLK, etc.)
The ADC-circuit looks like working OK and remains working OK.
The DSYNC1 output does show strange behavior, many DSYNC1 pulses are omitted.
We also see that the DCLK output reacts strange sometimes (the clock is not stable)
Q5: can it be explained why the ADC-circuit looks OK and the DSYNC/DCLK is NOK? (both use the same input clock!)
The problems became visible when we started production with a new date code (1706) all previously products where manufactured with Datecode 1440.
Q6: Is there something in the production of the AFE5401 chip changed that can be the cause our problems?
When there is more documentation available about the AFE5401, other than what’s present at the TI- website, please let me know.