Vcore Confusion

Hi,

I'm working with CC430F5xxx series nowadays. I want to use RF communication with it and i'm searching cc4305xxx user guide and example codes.

But two things are confused me...

1-) When i read the example codes for RF application, i saw they set Vcore to 2; but i want to use MCLK at 1 MHz so why should i have set Vcore to 2? Because datasheet says you can use CPU clock at 1 MHz with PMMCOREV = 0. İs it a Rf Application-specific thing?

       SetVCore(2);       // Increase PMMCOREV level to 2 for proper radio operation

2-) So if I have to use MCLK with proper PMMCOREV, why this example code doesn't use PMMCOREV register settings for 24 MHz? When i debugged it, i saw PMMCORE still 0 as default ( datasheet says, PMMCOREV must ve 3 for 24 MHZ DCO) but, program has run properly... They set DCOCLK to 24 MHz but they didn't change PMMCOREV registers.

//******************************************************************************
//   CC430F514x Demo - Software Toggle P1.0 with 12MHz DCO
//
//   Description: Toggle P1.0 by xor'ing P1.0 inside of a software loop.
//   ACLK is rought out on pin P2.0, SMCLK is brought out on P2.4, and MCLK
//   is brought out on pin P2.2.
//   ACLK = REFO = 32kHz, MCLK = SMCLK = 12MHz
//
//                 CC430F5147
//             -----------------
//         /|\|                 |
//          | |            P2.0 |-->ACLK
//          --|RST         P2.2 |-->MCLK
//            |            P2.4 |-->SMCLK
//            |                 |
//            |             P1.0|-->LED
//
//  G. Larmore
//  Texas Instruments Inc.
//  June 2012
//  Built with CCS v5.2 & IAR Embedded Workbench Version: 5.40.1
//******************************************************************************
#include  "msp430.h"

void main(void)
{
  WDTCTL = WDTPW+WDTHOLD;                   // Stop WDT
  P1DIR |= BIT0;                            // P1.0 output
 
  PMAPPWD = 0x02D52;                        // Get write-access to port mapping regs  
  P2MAP0 = PM_ACLK;                         // Map ACLK output to P2.0
  P2MAP2 = PM_MCLK;                         // Map MCLK output to P2.2
  P2MAP4 = PM_SMCLK;                        // Map SMCLK output to P2.4
  PMAPPWD = 0;                              // Lock port mapping registers  
   
  P2DIR |= BIT0 + BIT2 + BIT4;              // ACLK, MCLK, SMCLK set out to pins
  P2SEL |= BIT0 + BIT2 + BIT4;              // P2.0,2,4 for debugging purposes.
 
  UCSCTL3 |= SELREF_2;                      // Set DCO FLL reference = REFO
  UCSCTL4 |= SELA_2;                        // Set ACLK = REFO

  __bis_SR_register(SCG0);                  // Disable the FLL control loop
  UCSCTL0 = 0x0000;                         // Set lowest possible DCOx, MODx
  UCSCTL1 = DCORSEL_5;                      // Select DCO range 24MHz operation
  UCSCTL2 = FLLD_1 + 374;                   // Set DCO Multiplier for 12MHz
                                            // (N + 1) * FLLRef = Fdco
                                            // (374 + 1) * 32768 = 12MHz
                                            // Set FLL Div = fDCOCLK/2
  __bic_SR_register(SCG0);                  // Enable the FLL control loop

  // Worst-case settling time for the DCO when the DCO range bits have been
  // changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
  // UG for optimization.
  // 32 x 32 x 12 MHz / 32,768 Hz = 375000 = MCLK cycles for DCO to settle
  __delay_cycles(375000);
    
  // Loop until XT1,XT2 & DCO fault flag is cleared
  do
  {
    UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);
                                            // Clear XT2,XT1,DCO fault flags
    SFRIFG1 &= ~OFIFG;                      // Clear fault flags
  }while (SFRIFG1&OFIFG);                   // Test oscillator fault flag
    
  while(1)
  {
    P1OUT ^= BIT0;                          // Toggle P1.0
    __delay_cycles(600000);                 // Delay
  }
}