C5504 Asynchronous SRAM interface

Hi,

- I assume that in the C5504 User Guide Table 6-20 "EMIF Asynchronous Memory" in the case of SYSCLK = 150MHz E is equal to 6.66nS is that correct?

- Does the Asynchronous SRAM have the SDRAM 100MHz limitation?

- Can I change the Asynchronous SRAM parameters during system operation?

Thanks,

HR