Part Number:TMS320F28379D
Tool/software: Code Composer Studio
Hello
i am working to genarate the ePwm with 20Khz
and i have to control it by using Trip_zone
i find some examples in Cwere2000 i could not use the same way in my program
it is my program...
#include"F28x_Project.h"
#include"math.h"
#include<stdio.h>
#include<stdlib.h>
#define PWM_Prd 10000;
#define Phi1 1500; // (625)45 DEG PHASE
#define Phi2 1500; // (625)45 DEG PHASE
#define PI 3.14159265358979323846
Uint32 EPwm1TZIntCount;
Uint32 EPwm2TZIntCount;
void InitTzGpio(void);
voidInitEPwm1_2Example(void);
__interruptvoidepwm1_isr(void);
unsignedint i=0,m=0,k=0;
unsignedint a=0;
unsignedint b[101]={0};
voidmain(void)
{ InitSysCtrl();
InitEPwmGpio_TZ();
InitTzGpio();
for(m=0;m<100;m++)
{
a=sin(PI*0.02*m);
b[m]= 5000*a + 5000; //50% HALF SINE WAVE cycle.
}
b[100]=0;
InitGpio();
EALLOW;
InitEPwm1Gpio();
InitEPwm2Gpio();
InitEPwm3Gpio();
InitEPwm4Gpio();
InitEPwm5Gpio();
InitEPwm6Gpio();
GpioCtrlRegs.GPBDIR.bit.GPIO52 = 1;
EDIS;
DINT;
InitPieCtrl();
IER = 0x0000;
IFR = 0x0000;
InitPieVectTable();
EALLOW;
PieVectTable.EPWM1_INT = &epwm1_isr;
InitEPwm1_2Example();
EDIS;
IER |= M_INT3;
PieCtrlRegs.PIEIER3.bit.INTx1 = 1;
PieCtrlRegs.PIEIER3.bit.INTx2 = 1;
PieCtrlRegs.PIEIER3.bit.INTx3 = 1;
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM for(;;)
{ asm (" NOP"); }
}
__interruptvoidepwm1_isr(void)
{
GpioDataRegs.GPBDAT.bit.GPIO52 = 1;
if (EPwm1Regs.TZFLG.bit.OST == 0 && EPwm2Regs.TZFLG.bit.OST == 0)
a=sin(PI*0.02*i);
if (a>=0)
{
EPwm1Regs.CMPA.bit.CMPA =b[i];
EPwm1Regs.CMPB.bit.CMPB =b[i];
EPwm2Regs.CMPA.bit.CMPA =b[i];
EPwm2Regs.CMPB.bit.CMPB =b[i];
EPwm3Regs.CMPA.bit.CMPA =b[i];
EPwm3Regs.CMPB.bit.CMPB =b[i];
EPwm4Regs.CMPA.bit.CMPA =b[i];
EPwm4Regs.CMPB.bit.CMPB =b[i];
EPwm5Regs.CMPA.bit.CMPA =b[i];
EPwm5Regs.CMPB.bit.CMPB =b[i];
EPwm6Regs.CMPA.bit.CMPA =b[i];
EPwm6Regs.CMPB.bit.CMPB =b[i];
}
else
{
EPwm1Regs.CMPA.bit.CMPA =b[i];
EPwm1Regs.CMPB.bit.CMPB =b[i];
EPwm2Regs.CMPA.bit.CMPA =b[i];
EPwm2Regs.CMPB.bit.CMPB =b[i];
EPwm3Regs.CMPA.bit.CMPA =b[i];
EPwm3Regs.CMPB.bit.CMPB =b[i];
EPwm4Regs.CMPA.bit.CMPA =b[i];
EPwm4Regs.CMPB.bit.CMPB =b[i];
EPwm5Regs.CMPA.bit.CMPA =b[i];
EPwm5Regs.CMPB.bit.CMPB =b[i];
EPwm6Regs.CMPA.bit.CMPA =b[i];
EPwm6Regs.CMPB.bit.CMPB =b[i];
}
GpioDataRegs.GPBDAT.bit.GPIO52 = 0;
i++;
if (i==101)
{ i=0; }
EPwm1Regs.ETCLR.bit.INT = 1;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}
voidInitEPwm1_2Example()
{ // Enable INT Settings
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm1Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 3rd event
// // Setup counter mode //
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up and down
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
// Clock Settings
ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV =0;
ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV=0;
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
// // Setup shadowing //
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_IMMEDIATE;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_IMMEDIATE;
// Set compare A value
EPwm1Regs.AQCTLA.bit.PRD = AQ_SET; // Set PWM1A on event A, up
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Clear PWM1A on event B, down
EPwm1Regs.AQCTLB.bit.CBU = AQ_SET; // Set PWM1B on event A, up
EPwm1Regs.AQCTLB.bit.PRD = AQ_CLEAR; // Clear PWM1B on event B, down
//PWM settings
EPwm1Regs.TBPRD = PWM_Prd; // Set timer period 801 TBCLKs
EPwm1Regs.TBPHS.bit.TBPHS = 0; // Phase is 0
EPwm1Regs.TBCTR = 0;
// // Setup counter mode EPWM2 //
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up and down
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV =0;
ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV=0;
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;
// // Setup shadowing //
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_IMMEDIATE;
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_IMMEDIATE;
// // Set actions //
EPwm2Regs.AQCTLA.bit.PRD = AQ_CLEAR; // Set PWM1A on event A, up
EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // Clear PWM1A on event B, down
EPwm2Regs.AQCTLB.bit.PRD = AQ_SET; // Set PWM1B on event A, up
EPwm2Regs.AQCTLB.bit.CBU = AQ_CLEAR; // Clear PWM1B on event B, down
EPwm2Regs.TBPRD = PWM_Prd; // Set timer period 801 TBCLKs
EPwm2Regs.TBPHS.bit.TBPHS = 0; // Phase is 0
EPwm2Regs.TBCTR = 0;
// // Setup counter mode EPWM3 //
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up and down
EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading
EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV =0;
ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV=0;
EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;
// // Setup shadowing //
EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_IMMEDIATE;
EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_IMMEDIATE;
// // Set actions //
EPwm3Regs.AQCTLA.bit.PRD = AQ_SET; // Set PWM1A on event A, up
EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Clear PWM1A on event B, down
EPwm3Regs.AQCTLB.bit.PRD = AQ_CLEAR; // Set PWM1B on event A, up
EPwm3Regs.AQCTLB.bit.CBU = AQ_SET; // Clear PWM1B on event B, down
EPwm3Regs.TBPRD = PWM_Prd; // Set timer period 801 TBCLKs
EPwm3Regs.TBPHS.bit.TBPHS = 10000 - Phi1; // Phase is 0
EPwm3Regs.TBCTR = 0;
// // Setup counter mode EPWM4 //
EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up and down
EPwm4Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading
EPwm4Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV =0;
ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV=0;
EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV1;
// // Setup shadowing //
EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_IMMEDIATE;
EPwm4Regs.CMPCTL.bit.SHDWBMODE = CC_IMMEDIATE;
// // Set actions //
EPwm4Regs.AQCTLA.bit.PRD = AQ_CLEAR; // Set PWM1A on event A, up
EPwm4Regs.AQCTLA.bit.CAU = AQ_SET; // Clear PWM1A on event B, down
EPwm4Regs.AQCTLB.bit.PRD = AQ_SET; // Set PWM1B on event A, up
EPwm4Regs.AQCTLB.bit.CBU = AQ_CLEAR; // Clear PWM1B on event B, down
EPwm4Regs.TBPRD = PWM_Prd; // Set timer period 801 TBCLKs
EPwm4Regs.TBPHS.bit.TBPHS = 10000-Phi1; // Phase is 0
EPwm4Regs.TBCTR = 0;
// // Setup counter mode EPWM5 //
EPwm5Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up and down
EPwm5Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading
EPwm5Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm5Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV =0;
ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV=0;
EPwm5Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm5Regs.TBCTL.bit.CLKDIV = TB_DIV1;
// // Setup shadowing //
EPwm5Regs.CMPCTL.bit.SHDWAMODE = CC_IMMEDIATE;
EPwm5Regs.CMPCTL.bit.SHDWBMODE = CC_IMMEDIATE;
// // Set actions //
EPwm5Regs.AQCTLA.bit.PRD = AQ_SET; // Set PWM1A on event A, up
EPwm5Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Clear PWM1A on event B, down
EPwm5Regs.AQCTLB.bit.CBU = AQ_SET; // Set PWM1B on event A, up
EPwm5Regs.AQCTLB.bit.PRD = AQ_CLEAR; // Clear PWM1B on event B, down
EPwm5Regs.TBPRD = PWM_Prd; // Set timer period 801 TBCLKs
EPwm5Regs.TBPHS.bit.TBPHS = 10000 - Phi2; // Phase is 0
EPwm5Regs.TBCTR = 0;
// // Setup counter mode EPWM6 //
EPwm6Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up and down
EPwm6Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading
EPwm6Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm6Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV =0;
ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV=0;
EPwm6Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm6Regs.TBCTL.bit.CLKDIV = TB_DIV1;
// // Setup shadowing //
EPwm6Regs.CMPCTL.bit.SHDWAMODE = CC_IMMEDIATE;
EPwm6Regs.CMPCTL.bit.SHDWBMODE = CC_IMMEDIATE;
// // Set actions //
EPwm6Regs.AQCTLA.bit.PRD = AQ_CLEAR; // Set PWM1A on event A, up
EPwm6Regs.AQCTLA.bit.CAU = AQ_SET; // Clear PWM1A on event B, down EPwm6Regs.AQCTLB.bit.PRD = AQ_SET; // Set PWM1B on event A, up
EPwm6Regs.AQCTLB.bit.CBU = AQ_CLEAR; // Clear PWM1B on event B, down
EPwm6Regs.TBPRD = PWM_Prd; // Set timer period 801 TBCLKs
EPwm6Regs.TBPHS.bit.TBPHS = 10000 - Phi2; // Phase is 0
EPwm6Regs.TBCTR = 0;
}
here is the problem with initialization of TZGPIO.