Linux/AM3352: DDR3 initialization registers accessed twice in u-boot spl

Part Number:AM3352

Tool/software: Linux

Hi,

DDR3 initialization in u-boot SPL requires a gap of 500us between DDR_RESET and CKE, which is accomplished by setting an initial refresh control register value 0x3100. After reset, the refresh control register is set to the actual refresh value. This is done in config_sdram in the if(regs->zq_config) bracket. However there is a second time that these registers are accessed right after. We think this should be in an else bracket. Is that correct?

Otherwise we are accessing the registers twice, which should not be the intent.

Can we correct this?

Regards,

--Gunter