Part Number:MSP430F6459
Hi everyone,
In LPM3 mode, ACLK should still work. But the following code in MSP430F6459 tells it will shut down ACLK( source from XT1=32KHz).
Besides, if my PCBA connet with MSP-Fet430UIF, ACLK is fine(LPM3).
Need your help on this.
Thanks.
Best Regards,
SeaFesse
#include <msp430f6459.h> void main(void) { WDTCTL = WDTPW | WDTHOLD; // Stop WDT P1DIR |= BIT0; P1SEL |= BIT0; //P1.0----ACLK output PJDIR |= BIT2; // PJSEL &=~BIT2; while(BAKCTL & LOCKBAK) // Unlock XT1 pins for operation BAKCTL &= ~(LOCKBAK); // Setup UCS UCSCTL3 |= SELREF__XT1CLK; // Set DCO FLL reference = XT1 UCSCTL4 |= SELA__XT1CLK; // Set ACLK = XT1 __bis_SR_register(SCG0); // Disable the FLL control loop UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx UCSCTL1 = DCORSEL_5; // Select DCO range 16MHz operation UCSCTL2 = FLLD_1 | 243; // Set DCO Multiplier for 8MHz // (N + 1) * FLLRef = Fdco // (243 + 1) * 32768 = 8MHz // Set FLL Div = fDCOCLK/2 __bic_SR_register(SCG0); // Enable the FLL control loop // Worst-case settling time for the DCO when the DCO range bits have been // changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx // UG for optimization. // 32 x 32 x 8 MHz / 32,768 Hz = 250000 = MCLK cycles for DCO to settle __delay_cycles(250000); // Loop until XT1, XT2 & DCO fault flag is cleared do { UCSCTL7 &= ~(XT2OFFG | XT1LFOFFG | DCOFFG); // Clear XT2,XT1,DCO fault flags SFRIFG1 &= ~OFIFG; // Clear fault flags } while (SFRIFG1 & OFIFG); // Test oscillator fault flag while(1) { __bis_SR_register(LPM3_bits | GIE); // Enter LPM0, interrupts enabled __no_operation(); // For debugger } }