Part Number:TMS320DM8168
My customer need to get information regarding the DIVCLK which is a part of the PCIe module.
As he see, DIVCLK is reported as not running, randomly (different for each power up), and without any correlation to our PCIe issue we are currently investigating (Link/Reading from BAR registers).
What can be the cause that it is not running? What are the anticipated outcome of such scenario?
From the documentation they have and from answer they got from the TI E2E they understand that this clock must be enabled and must be running for proper operation of the PCIe module.
They did not see any explanation for this "div by 5" PLL clock (DIVCLK) in the documentation, only general explanation. is this clock is the 250MHz clock mentioned?
Does jitter on the REFCLK input clock (although it is “locked”, bit[8]LOCK=’1’) can cause the lack of the DIVLCK?
Please help