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TMS320F28377D: The ADC module configue issue on TMS320F28377X.

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Part Number:TMS320F28377D

When I configure the ADC module on 28377D,I hope to configure the A port as 16 bit mode and B port as 12 bit mode,Can it realize?

When I do it as above,I can read the data from A port results...but could not read from B port.In this situation,AdcbRegs.RESULT0..15 all are zero. but why?

The Configure Code as follows:

void InitADC(void)
{
unsigned int i;

EALLOW;

//part1:set ADCCLK divider to /4
AdcaRegs.ADCCTL2.bit.PRESCALE = 6;
AdcbRegs.ADCCTL2.bit.PRESCALE = 6;
AdccRegs.ADCCTL2.bit.PRESCALE = 6;
AdcdRegs.ADCCTL2.bit.PRESCALE = 6;

//part2:16bit Differential ADC mode.

AdcSetMode(ADC_ADCA, ADC_RESOLUTION_16BIT, ADC_SIGNALMODE_DIFFERENTIAL);
AdcSetMode(ADC_ADCC, ADC_RESOLUTION_16BIT, ADC_SIGNALMODE_DIFFERENTIAL);
AdcSetMode(ADC_ADCB, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);
AdcSetMode(ADC_ADCD, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);

//part3:Set pulse positions to late about INTFlag after ADC converted.
AdcaRegs.ADCCTL1.bit.INTPULSEPOS = 1;
AdcbRegs.ADCCTL1.bit.INTPULSEPOS = 1;
AdccRegs.ADCCTL1.bit.INTPULSEPOS = 1;
AdcdRegs.ADCCTL1.bit.INTPULSEPOS = 1;

//part4:power up the ADC
AdcaRegs.ADCCTL1.bit.ADCPWDNZ = 1;
AdcbRegs.ADCCTL1.bit.ADCPWDNZ = 1;
AdccRegs.ADCCTL1.bit.ADCPWDNZ = 1;
AdcdRegs.ADCCTL1.bit.ADCPWDNZ = 1;

//part5:delay for > 1ms to allow ADC time to power up
for(i = 0; i < 1000; i++){asm(" RPT#255 || NOP");}

//part6:SOCx configure for A/B/C/D ports.

AdcaRegs.ADCSOC0CTL.bit.CHSEL = 2; //SOC0 will convert adcina0/a1
AdcaRegs.ADCSOC0CTL.bit.ACQPS = ADCACQPS; //sample and hold time window is 100 SYSCLK cycles
AdcaRegs.ADCSOC0CTL.bit.TRIGSEL = ADCTRIGSEL;

//A4/5->VoltageUdc
AdcaRegs.ADCSOC1CTL.bit.CHSEL = 4; //SOC1 will convert adcina2/a3
AdcaRegs.ADCSOC1CTL.bit.ACQPS = ADCACQPS; //sample and hold time window is 100 SYSCLK cycles
AdcaRegs.ADCSOC1CTL.bit.TRIGSEL = ADCTRIGSEL;

//B:B0/1/2/3->SPD
AdcbRegs.ADCSOC0CTL.bit.CHSEL = 0; //SOC0 will convert adcinb0
AdcbRegs.ADCSOC0CTL.bit.ACQPS = ADCACQPS2; //sample and hold time window is 100 SYSCLK cycles
AdcbRegs.ADCSOC0CTL.bit.TRIGSEL = ADCTRIGSEL;

//C:C2/3->CurrentW
AdccRegs.ADCSOC0CTL.bit.CHSEL = 2; //SOC0 will convert adcin14/15
AdccRegs.ADCSOC0CTL.bit.ACQPS = ADCACQPS; //sample and hold time window is 100 SYSCLK cycles
AdccRegs.ADCSOC0CTL.bit.TRIGSEL = ADCTRIGSEL;

AdcaRegs.ADCINTSEL1N2.bit.INT1SEL = 1; //end of SOC1 will set INT1 flag
AdcaRegs.ADCINTSEL1N2.bit.INT1E = 1; //Enable INT1 flag
AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //Make sure INT1 flag is cleared

EDIS;


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