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c6713 EDMA+MCBSP to link AIC23 problems

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Hello, I have a question. Now I use EDMA+MCBSP with TMS320C6713B to link AIC23B and send data to headphone. When I have hardware emulation, there is no problem and the result is perfect. But when I load the hex file in the external FLASH, it has problems.

First, I have three DSP boards, but only one board can run rightly, in other boards the EDMA will not come into the ISR.(I have two leds to test. One led test the timer0's ISR, the other which is not flash  test  EDMA's interrupt ) I am sure the AIC23B is set rightly. I have looked the wave through the OSC.

Second, the board which runs rightly will be channel swapping sometimes.

The configuration I am using is the following:

#include <stdio.h>

#include <string.h>

#include <stdlib.h>

#include <math.h>

#include <ctype.h>

//CSL

#include <csl.h>

#include <csl_cache.h>

#include <csl_edma.h>

#include <csl_timer.h>

#include <csl_irq.h>

#include <csl_mcbsp.h>

#include <csl_edma.h>

……

short gBufferXmtPing[BUFFSIZE];  // Transmit PING buffer

short gBufferXmtPong[BUFFSIZE];  // Transmit PONG buffer

……

#define PING  0         

#define PONG  1

EDMA_Handle hEdmaXmt;            // EDMA channel handles

EDMA_Handle hEdmaReloadXmtPing;

EDMA_Handle hEdmaReloadXmtPong;

short gXmtChan;

unsigned char xmtdone = 0 ;

short pingORpong=PING;

/* Transmit side EDMA configuration */

EDMA_Config gEdmaConfigXmt = { 

    EDMA_FMKS(OPT, PRI, HIGH)          |  // Priority

    EDMA_FMKS(OPT, ESIZE, 16BIT)       |  // Element size

    EDMA_FMKS(OPT, 2DS, NO)            |  // 2 dimensional source?

    EDMA_FMKS(OPT, SUM, INC)           |  // Src update mode

    EDMA_FMKS(OPT, 2DD, NO)            |  // 2 dimensional dest

    EDMA_FMKS(OPT, DUM, NONE)          |  // Dest update mode

    EDMA_FMKS(OPT, TCINT, YES)         |  // Cause EDMA interrupt?

    EDMA_FMKS(OPT, TCC, OF(0))         |  // Transfer complete code

    EDMA_FMKS(OPT, LINK, YES)          |  // Enable link parameters?

    EDMA_FMKS(OPT, FS, NO),               // Use frame sync?

 

    (Uint32)&gBufferXmtPing,              // Src address

 

    EDMA_FMK (CNT, FRMCNT, NULL)       |  // Frame count

    EDMA_FMK (CNT, ELECNT, BUFFSIZE),     // Element count

   

    EDMA_FMKS(DST, DST, OF(0)),           // Dest address

 

    EDMA_FMKS(IDX, FRMIDX, DEFAULT)    |  // Frame index value

    EDMA_FMKS(IDX, ELEIDX, DEFAULT),      // Element index value

 

    EDMA_FMK (RLD, ELERLD, NULL)       |  // Reload element

    EDMA_FMK (RLD, LINK, NULL)            // Reload link

};

void initEdma(void)

{

    /* Configure transmit channel */

    hEdmaXmt = EDMA_open(EDMA_CHA_XEVT0, EDMA_OPEN_RESET);  // get hEdmaXmt handle and reset channel

    hEdmaReloadXmtPing = EDMA_allocTable(-1);               // get hEdmaReloadXmtPing handle

    hEdmaReloadXmtPong = EDMA_allocTable(-1);               // get hEdmaReloadXmtPong handle

   

    gEdmaConfigXmt.dst = MCBSP_getXmtAddr(hMcbsp0);         // set the desination address to McBSP1 DXR

       

    gXmtChan = EDMA_intAlloc(-1);                           // get an open TCC

    gEdmaConfigXmt.opt |= EDMA_FMK(OPT,TCC,gXmtChan);       // set TCC to gXmtChan

       

    EDMA_config(hEdmaXmt, &gEdmaConfigXmt);                 // then configure the registers

    EDMA_config(hEdmaReloadXmtPing, &gEdmaConfigXmt);       // and the reload forPing

   

    gEdmaConfigXmt.src = EDMA_SRC_OF(gBufferXmtPong);       // change the structure to have a source of Pong

    EDMA_config(hEdmaReloadXmtPong, &gEdmaConfigXmt);       // and configure the reload for Pong       

   

    EDMA_link(hEdmaXmt,hEdmaReloadXmtPong);                 // link the regs to Pong

    EDMA_link(hEdmaReloadXmtPong,hEdmaReloadXmtPing);       // link Pong to Ping

    EDMA_link(hEdmaReloadXmtPing,hEdmaReloadXmtPong);       // and link Ping to Pong   

       

    /* Enable interrupts in the EDMA controller */

    EDMA_intClear(gXmtChan);   

 

    EDMA_intEnable(gXmtChan);                               // enable EDMA interrupts (CIER)

 

    EDMA_enableChannel(hEdmaXmt);                           // enable EDMA channel

   

    /* Do a dummy write to generate the first McBSP transmit event */

    MCBSP_write(hMcbsp0, 0);

}

/* McBSP codec data channel configuration */

static MCBSP_Config mcbspCfg0 = {

        MCBSP_FMKS(SPCR, FREE, NO)              |

        MCBSP_FMKS(SPCR, SOFT, NO)              |

        MCBSP_FMKS(SPCR, FRST, YES)             |

        MCBSP_FMKS(SPCR, GRST, YES)             |

        MCBSP_FMKS(SPCR, XINTM, XRDY)           |

        MCBSP_FMKS(SPCR, XSYNCERR, NO)          |

        MCBSP_FMKS(SPCR, XRST, YES)             |

        MCBSP_FMKS(SPCR, DLB, OFF)              |

        MCBSP_FMKS(SPCR, RJUST, RZF)            |

        MCBSP_FMKS(SPCR, CLKSTP, DISABLE)       |

        MCBSP_FMKS(SPCR, DXENA, OFF)            |

        MCBSP_FMKS(SPCR, RINTM, RRDY)           |

        MCBSP_FMKS(SPCR, RSYNCERR, NO)          |

        MCBSP_FMKS(SPCR, RRST, YES),

 

        MCBSP_FMKS(RCR, RPHASE, SINGLE)         |

        MCBSP_FMKS(RCR, RFRLEN2, DEFAULT)       |

        MCBSP_FMKS(RCR, RWDLEN2, DEFAULT)       |

        MCBSP_FMKS(RCR, RCOMPAND, MSB)          |

        MCBSP_FMKS(RCR, RFIG, NO)               |

        MCBSP_FMKS(RCR, RDATDLY, 0BIT)          |

        MCBSP_FMKS(RCR, RFRLEN1, OF(1))         |

        MCBSP_FMKS(RCR, RWDLEN1, 16BIT)         |

        MCBSP_FMKS(RCR, RWDREVRS, DISABLE),

 

        MCBSP_FMKS(XCR, XPHASE, SINGLE)         |

        MCBSP_FMKS(XCR, XFRLEN2, DEFAULT)       |

        MCBSP_FMKS(XCR, XWDLEN2, DEFAULT)       |

        MCBSP_FMKS(XCR, XCOMPAND, MSB)          |

        MCBSP_FMKS(XCR, XFIG, NO)               |

        MCBSP_FMKS(XCR, XDATDLY, 0BIT)          |

        MCBSP_FMKS(XCR, XFRLEN1, OF(1))         |

        MCBSP_FMKS(XCR, XWDLEN1, 16BIT)         |

        MCBSP_FMKS(XCR, XWDREVRS, DISABLE),

       

        MCBSP_FMKS(SRGR, GSYNC, DEFAULT)        |

        MCBSP_FMKS(SRGR, CLKSP, DEFAULT)        |

        MCBSP_FMKS(SRGR, CLKSM, DEFAULT)        |

        MCBSP_FMKS(SRGR, FSGM, DEFAULT)         |

        MCBSP_FMKS(SRGR, FPER, DEFAULT)         |

        MCBSP_FMKS(SRGR, FWID, DEFAULT)         |

        MCBSP_FMKS(SRGR, CLKGDV, DEFAULT),

 

        MCBSP_MCR_DEFAULT,

        MCBSP_RCER_DEFAULT,

        MCBSP_XCER_DEFAULT,

 

        MCBSP_FMKS(PCR, XIOEN, SP)              |

        MCBSP_FMKS(PCR, RIOEN, SP)              |

        MCBSP_FMKS(PCR, FSXM, EXTERNAL)         |

        MCBSP_FMKS(PCR, FSRM, EXTERNAL)         |

        MCBSP_FMKS(PCR, CLKXM, INPUT)           |

        MCBSP_FMKS(PCR, CLKRM, INPUT)           |

        MCBSP_FMKS(PCR, CLKSSTAT, DEFAULT)      |

        MCBSP_FMKS(PCR, DXSTAT, DEFAULT)        |

        MCBSP_FMKS(PCR, FSXP, ACTIVEHIGH)       |

        MCBSP_FMKS(PCR, FSRP, ACTIVEHIGH)       |

        MCBSP_FMKS(PCR, CLKXP, FALLING)         |

        MCBSP_FMKS(PCR, CLKRP, RISING)

};

 

void initMcbsp0()

{

    /* Open the codec data McBSP */

    hMcbsp0 = MCBSP_open(MCBSP_DEV0, MCBSP_OPEN_RESET);

 

    /* Configure the codec to match the AIC23 data format */

    MCBSP_config(hMcbsp0, &mcbspCfg0);

 

    /* Start the McBSP running */

    MCBSP_start(hMcbsp0, MCBSP_XMIT_START | MCBSP_RCV_START |

        MCBSP_SRGR_START | MCBSP_SRGR_FRAMESYNC, 220);

}

void initMcbsp1()

{

……

}

 

void main(){

       CSL_init();                          /* initialize the CSL library */

       DEVCFG = 0x0;

       Init_PLL();                          /*initialize PLL*/

       Init_EMIF();                         /*initialize emif */

       for(i=0;i<BUFFSIZE;i++)

       {

              gBufferXmtPing[i] = 0 ;

              gBufferXmtPong[i] = 0 ;

       }

       initMcbsp0();

       initMcbsp1();

       ……                                           

       IRQ_globalDisable();                 /* Disable all interrupts        */

       initEdma();

       IER=1;                               /* Disable all interrupts except NMI   */

       IRQ_setVecs((void *)0x800);             /* point to the IRQ vector table */

      ICR = 0x0ffff ;

      IER |= 0x4133;                           /*enable EXINT4 EXINT5 TIME0 EDMA interrupt*/

      IRQ_globalEnable();                  /*enable all interrupts*/ 

       ……

       while(1)

       {

       ……

       }

}

Thanks a lot for your time. 

Regards, 
HTS 


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