AM5728: Configuring EMIF(s) to use solely EMIF2

Part Number:AM5728

Hello,

We have a custom designed PCB with an AM5728, we are having issues with our SPL failing to launch U-Boot and we suspect it is an issue with the EMIF configs.

I have followed SPRAC36A closely to populate configuration values, however our configuration seems to be different than the typical as we use EMIF2 and not EMIF1. EMIF2 was selected for PCB layout reasons, and before design the TRM was consulted to look for any issues with using just EMIF2 and not EMIF1, there was no indication found that this was not allowed.

When 1 EMIF interface is selected in the EMIF Config document it seems to default settings to EMIF1. Namely it looks like the dmm_lisa_map_x [1:4] registers default to EMIF1.

It is also of note that values for emif_ddr_ext_phy_ctrl_x [1:5] included in the emif_regs structs are not produced by the spreadsheet, is there anything that we should be doing with them?

See below the input data used:

Output configuration data:

const struct dpll_params AM572x_DDR3L_532MHz_6728_rev00_pll_params = {

    .m = 266,

    .n = 4,

    .m2 = 2,

    .m4_h11 = 8

};

const struct ctrl_ioregs AM572x_DDR3L_532MHz_6728_rev00_ctrl_ioregs = {

    .ctrl_ddr3ch = 0x80808080,

    .ctrl_ddrch = 0x40404040,

    .ctrl_ddrio_0 = 0x00094A40,

    .ctrl_ddrio_1 = 0x04A52000,

    .ctrl_emif_sdram_config_ext = 0x0000C123

};

const struct dmm_lisa_map_regs AM572x_DDR3L_532MHz_6728_rev00_dmm_regs = {

    .dmm_lisa_map_0 = 0x00000000,

    .dmm_lisa_map_1 = 0x00000000,

    .dmm_lisa_map_2 = 0x80400100, <- original value

    .dmm_lisa_map_3 = 0xFF020100, <- original value

    .dmm_lisa_map_2 = 0x80400200, <- Attempted fix for EMIF2

    .dmm_lisa_map_3 = 0xFF020200, <- Attempted fix for EMIF2

    .is_ma_present = 0x1

};

const struct emif_regs AM572x_DDR3L_532MHz_6728_rev00_emif_regs = {

    .sdram_config_init = 0x61851A32,

    .sdram_config = 0x61851A32,

    .sdram_config2 = 0x00000000,

    .ref_ctrl = 0x000040F1,

    .ref_ctrl_final = 0x00001035,

    .sdram_tim1 = 0xCCCF36AB,

    .sdram_tim2 = 0x30457FDA,

    .sdram_tim3 = 0x407F83A8,

    .read_idle_ctrl = 0x00050000,

    .zq_config = 0x5007190B,

    .temp_alert_config = 0x00000000,

    .emif_rd_wr_lvl_rmp_ctl = 0x80000000,

    .emif_rd_wr_lvl_ctl = 0x00000000,

    .emif_ddr_phy_ctlr_1_init = 0x0024400B,

    .emif_ddr_phy_ctlr_1 = 0x0E24400B,

    .emif_rd_wr_exec_thresh = 0x00000305

};

Thanks,

Chad