Part Number:TMS320F28075
Hello,
I have a question about interrupt generation. I am configuring my ePWM's Digital Compare submodule. Here trip 11 is configured to DCAEVT1 to cause a trip on ePWM6.
My question is, which interrupt does this DCAEVT1 generates?
I looked at the TZENT register and it says using One shot (OST) causes EPWMx_TZINT PIE Interrupt. So, similarly what interrupt occurs on trip event DCAEVT1.
I have written my configurations along with little info about TZENT from user manual.
/*************** From TZENT register: *******************/
Bit3 DCAEVT1 R/W 0h
Digital Compare Output A Event 1 Interrupt Enable
0: Disabled
1: Enabled
Reset type: SYSRSn
Bit2 OST R/W 0h
Trip-zone One-Shot Interrupt Enable
0: Disable one-shot interrupt generation
1: Enable Interrupt generation
a one-shot trip event will cause a EPWMx_TZINT PIE interrupt.
Reset type: SYSRSn
/*************** MY configurations *******************/
//Configure EPWM output A & B to go low on trip. EPwm6Regs.TZCTL.bit.TZA = TZ_FORCE_LO; EPwm6Regs.TZCTL.bit.TZB = TZ_FORCE_LO; //Configure DCA to be TRIP11 EPwm6Regs.TZDCSEL.bit.DCAEVT1 = TZ_DCBH_HI; EPwm6Regs.DCTRIPSEL.bit.DCAHCOMPSEL = 0xA; // Trip11 EPwm6Regs.DCAHTRIPSEL.bit.TRIPINPUT11 = 0; // Single trip input; Not ORed //Configure DCA as DCAEVT1 EPwm6Regs.TZSEL.bit.DCAEVT1 = 1; // Enable //Configure DCA path to be unfiltered & async EPwm6Regs.DCACTL.bit.EVT1SRCSEL = DC_EVT1; EPwm6Regs.DCACTL.bit.EVT1FRCSYNCSEL = DC_EVT_ASYNC; // Clear trip flags EPwm6Regs.TZCLR.bit.DCAEVT1 = 1; // Writing 1 clears trip flags. EPwm6Regs.TZCLR.bit.INT = 1; //Enable DCB interrupt EPwm6Regs.TZEINT.bit.DCAEVT1 = 1;
I appreciate your help.
Thanks
Sagar