Part Number:UCD3138
The UCD3138 Technical Reference Manual on page 402 suggests using this statement to clear the 16 bit timer interrupt flag CMP0_INT_FLAG:
"TimerRegs.T16PWM1CMPCTRL.all | = 3;"
This statement works, but there are several other options which will work as well.
The general statement is on page 418:
"This bit is cleared by writing ‘1’ to this bit or by rewriting T16PWMxCMP0DAT."
Normally, the interrupt bit is cleared at the end of the timer interrupt, so that the timer interrupt will not reenter immediately.
However, if the CMP0_INT_ENA bit is used to disable interrupts in the background mode, interrupts may be missed.
With the ARM7, bit setting and clearing is not atomic, meaning it can be interrupted between the read and the write. It is always dangerous on the UCD to have interrupt and background working on different bits in the same register. However, in this case, even if bit setting was atomic, this would still be an issue.
Here is the sequence which causes the problem:
1. The background code clears the CMP0_INT_ENA bit.
2. During the background code protected from the interrupt, the timer times out, and the CMP0_INT_FLAG is set.
3. When the background code which sets the CMP0_INT_ENA bit is executed, it also reads and writes the 1 in the CMP0_INT_FLAG bit. This clears the CMP0_INT_FLAG bit.
This causes the interrupt to be missed.
If it is necessary to protect the background code from this interrupt, some other means should be used - either a generic interrupt disable, or a clearing of the interrupt enable flag for the relevant PWM in the Central Interrupt Module.