Part Number:TMS320C6748
Hi experts,
We need to rate the max. latency (#wait cycles inserted) on the HPI with the On-Chip (128kB) Shared RAM as the HPI data resource. In our application this RAM (aka L3) is shared between HPI and DSP CPU (cache enabled), both being bus masters.
Arbitrating between requests:
On condition of default master priority settings (HPI lower than DSP CPU), if two concurrent requests to the SRAM arrive, the one with the higher priority level wins the arbitration. For the Switch Central Resources arbitration occurs at burst size boundaries (valuable info found in wiki 'OMAP-L1x/C674x/AM1x SoC Architectural Overview’).
My question: does that mean, that a higher priority request will block any lower one for the full time it takes to transfer its 'burst' (e.g. L2 cache: Burst size=Line size=128 bytes) ?
Calculating the effective latency:
In search for some latency details on the data access to (L3)SRAM, I have been referred to the wiki ‘Shared RAM Access Considerations on OMAPL1x/C674x/AM1x’: the figure being quoted there for accesses made by the CPU is Latency (cycles).
My question: Does these cycles refer to the clock of DSP (PLL0_SYSCLK1) or Shared RAM (PLL0_SYSCLK2) ?
Btw. Do you know any T.I. technical document containing more detailed infos on this On-Chip timing/latency topics?
t.y.i.a.
Regards,
Ludger
