I am working on a LIN-Projekt but couldn't find an example to work with. I describe the conecpt in short here, maybe it starts a helpful discussion and/or answers my open questions.
Init (generated with HalCoGen 3.6.0)
TX/RX-Mask both set to 0xFF HGEN = 1 -> all ID's should be accepted. I am using master mode, my guess is that I'll get interrupts for all ID's even tough my ECU sends them since it's the master. Does it mean that any ID generates an ID_RX and an ID_TX interrupt because there is no masking?
ID-Interrupt, RX-INT enabled, TX-INT can't be enabled in HalCoGen (bug?), enabled it by hand in my code
Header-Task
periodically calls linSendHeader(linREG, id); to generate appropriate headers
LIN-Taks
set up data for tx-respone or copy data from rx-response
Interrupt Routine
check what caused the interrupt
if ID interrupt: read ID and notify LIN-TASK.
if TX_RDY inerrupt: linSetLength(); linSend(); / / writing to last byte of lin->TDx clears this interrupt
if RX_RDY interrupt: linSetLength(); linGetData(); // reading of last byte from lin->RDx[i] clears this interrupt
exit -> read linREG->INTVECT0 to clear ID interrupt
In general I find it confusing how to clear interrupts. Is it appropriate to write a 1 to the the corresponding bit in the flag register to clr the interrupt, or is it necessary to read the linREG->INTVECT0 register? If reading the flag is appropriate it would make more sense to handle the tx/rx-response on task level, handling it on interrupt level and copying it on task level creates overhead. If clearing the interrupt by writing a 1 to the bit in the flag register does the job then I would be wondering what the INTVECT0 does.
Regards,
Jürgen