Part Number:TMS320F28379D
Tool/software: TI C/C++ Compiler
Hello there,
i have started to use the LAUNCHXL-F28379D.
The concept is to have all "IO things" on CPU1 while having all the algorithm on CPU2.
So the idea is to place all ADC results and all the other stuff in arrays which are then tied to global shared ram with a #pragma DATASECTION.
Of course the code in the main.cpp files of ech project are a bit different, but the #pragma DATASECTON´s are in the same order.
I have investgated the .map file and actually the arrays on the CPU´s don´t have the same order, see attachments at the bottom (mapfile, cmd files, pragma SECTIONS).
The projects are both running on optimization level -O2, have also tried the "off" condition with same result.
My question is how can i make sure the arrays are arranges equally on both CPU´s map files?
One idea could be to scramble the Global Shared RAM in chunks exactly the size of each array and define a name in the SECTION area of the map file. But this would mean some typing efford and more important a higher risk to forget something, whan an array gets changed in size...
Are there other approaches than that?
best regards,
Jasson
(Please visit the site to view this file)
(Please visit the site to view this file)
(Please visit the site to view this file)
(Please visit the site to view this file)