L1/L2 memory protection documentation

I am looking for documentation that describes the L1/L2 memory protection hardware and registers in an OMAP-L137.  All I have found is Table 2-3 in the omap-l137.pdf (SPRS563E).  This memory protection appears to be different from the L3/EMIF memory protection described in the TRM.

What I am really attempting to do is allow the ARM to have access to a range of addresses in L2 memory.

I'd appreciate if I could be pointed in the right direction.

Thanks,

Chris