Problem with SPI reads

-I'm using the lm4f230h5qr (which would be the TM4C123GH6PM). 

-Using code composer studio version 5.3

-Using my own board

I have two SPI slaves on two separate SSI modules, SSI0 and SSI1. The slave configured on SSI0 works fine. I can read from it and write to it.

The slave on SSI1 is, hardware and software wise, set up the same as the slave on SSI0. The problem is that when I do a read (in spi mode), only 0s get put into the receive FIFO. The correct number of items get placed in the FIFO, but as I said they contain all 0s.

I have probed all SPI lines at the microcontroller and I can verify that clock, chip select, and both data lines are working as expected. The slave does reply with the correct response. So the MISO pin does see the correct signalling.

here are some specifics:

-I am not using the Fss pin as the slave select for this slave. I'm using a GPIO pin on port A. I have not configured the Fss pin in any special way, its just unused.

-2.5 MHz sclk frequency with 8 bit data width.

Here is my code:

Hardware INIT:

SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);        // Accelerometer CS pin on this port

GPIOPinTypeGPIOOutput(GPIO_PORTA_BASE, GPIO_PIN_6); // Accelerometer CS pin

GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_6, 0xFF);    // Initialize the pin to a high state

// Initialize SPI
SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI1); // Enable SSI 1 peripheral
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF); // Enable Port F

// Configure SPI I/O
GPIOPinConfigure(GPIO_PF2_SSI1CLK);
GPIOPinConfigure(GPIO_PF3_SSI1FSS);
GPIOPinConfigure(GPIO_PF0_SSI1RX);
GPIOPinConfigure(GPIO_PF1_SSI1TX);

GPIOPinTypeSSI(GPIO_PORTF_BASE, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3);

SSIConfigSetExpClk(SSI1_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_3, SSI_MODE_MASTER, 2500000, 8);

SSIEnable(SSI1_BASE); // Enable SSI 1

Code to read from the slave:

uint32_t data1 = 0;
uint32_t data2 = 0;

while(SSIDataGetNonBlocking(SSI1_BASE, &data1));        // Clear out FIFO

GPIOPinWrite(acc.io_port, acc.cs_pin, 0x00);            // Assert the chip select
SSIDataPut(SSI1_BASE, reg_name | 0x80);                 // Send over the reg. address and set read bit

SSIDataPut(SSI1_BASE, 0x00);                            // Send 0s, only interested in received data
while(SSIBusy(SSI1_BASE));                              // Wait until sending is complete
GPIOPinWrite(acc.io_port, acc.cs_pin, 0xFF);            // Deassert the chip select

SSIDataGet(SSI1_BASE, &data1);                          // Pop FIFO and store item in data1
SSIDataGet(SSI1_BASE, &data2);                          // Pop FIFO and store item in data2

'acc' is just a struct with the io port with the cs pin, the cs pin number.

when I do the read, I get the proper signals on the proper pins, but data1 and data2 are both 0s. I know the correct number of items are in the fifo, because if I add a third SSIDataGet at the end, it will block indefinitely since nothing is in the fifo.

here's a snapshot of the spi signals:

Any ideas why I'm not getting the 0A in the receive fifo? Like I said, I have a slave on SSI0 (that even has the same CPHA and CPOL) that works fine, only it uses the Fss of the ssi port.

Thanks