Part Number:TMS320C6670
Hi,
My configuration is:
- SYSBIOS 6.35.4.50,
- IPC 1.25.3.15,
- MCSDK PDK TMS320C6670 1.1.2.6,
- TMDXEVM6670L_EVM board.
I'm trying by using qmssIpcBenchmark example put code and data to DDR3 memory and turn on cache. With default platform ti.platforms.evm6670 everything is working well.
All data (code, data and stack) are in SDRAM. After run, console output looks like this:
[C66xx_0] timerFreq.lo = 1000000000. timerFreq.hi = 0
cpuFreq.lo = 1000000000. cpuFreq.hi = 0
Core ("CORE0") starting
-----------------------Initializing---------------------------
Core 0 : L1D cache size 4. L2 cache size 0.
address of monolithicDesc[] = 0xc050000. Converted=0x1c050000
Core 0 : Memory region 0 inserted
[C66xx_1] timerFreq.lo = 1000000000. timerFreq.hi = 0
cpuFreq.lo = 1000000000. cpuFreq.hi = 0
Core ("CORE1") starting
localQueueName=CORE1. nextQueueName=CORE0. prevQueueName=CORE0
[C66xx_0] localQueueName=CORE0. nextQueueName=CORE1. prevQueueName=CORE1
tsk0 starting
[C66xx_1] tsk0 starting
[C66xx_0] tsk0. selfproc=0 nextQueueName (CORE1) openned, nextQueueId=65536
tsk0. selfProc=0 calling MessageQ_put(nextQueueName=CORE1). msg=0xc002a80
[C66xx_1] tsk0. selfproc=1 nextQueueName (CORE0) openned, nextQueueId=0
[C66xx_0] ======== SYSTEM ATTRIBUTES ========
Device name: TMS320C6670
Processor names: CORE0,CORE1
CPU Freq: 1000 MHz
Timer Freq: 1000 MHz
======== BENCHMARK ATTRIBUTES ========
MessageQ setup delegate: ti.transport.ipc.qmss.transports.TransportQmssSetup
Number of processors: 2
Number of messages received: 93
Build profile: debug
======== MESSAGEQ BENCHMARK RESULTS ========
Average 1-way latency: 3151 (cycles/msg) 3151 (ns/msg)
Maximum 1-way latency: 3160 (cycles/msg) (# 3) 3160 (ns/msg)
Minimum 1-way latency: 3144 (cycles/msg) (# 29) 3144 (ns/msg)
Standard deviation: 3 (cycles/msg)
Total time elapsed: 554672 (cycles) 554 (us)
Throughput via upfront allocation: Allocate all messages up front, sync cores, send all messages from core 0 to core 1
[C66xx_1] Core 1. msgs Received= 2000 time=2318425 (cycles - 2318 us). thrput=862812 [msgs/s]
cycles/msg = 1159When I put code and data to DDR3 memory by creating new platform file and then run example, I've got error in console:
[C66xx_0] timerFreq.lo = 1000000000. timerFreq.hi = 0
cpuFreq.lo = 1000000000. cpuFreq.hi = 0
Core ("CORE0") starting
-----------------------Initializing---------------------------
Core 0 : L1D cache size 4. L2 cache size 4.
address of monolithicDesc[] = 0xc050000. Converted=0x1c050000
Core 0 : Memory region 0 inserted
[C66xx_1] timerFreq.lo = 1000000000. timerFreq.hi = 0
cpuFreq.lo = 1000000000. cpuFreq.hi = 0
Core ("CORE1") starting
ti.sysbios.family.c64p.Hwi: line 188: E_alreadyDefined: Hwi already defined: intr# 5
xdc.runtime.Error.raise: terminating execution
Below is a print screen showing new platform configuration:
New platform name is C6670_with_DDR3.
In project properties: General->RTSC->Platform I've changed platform to C6670_with_DDR3:
I also added to cfg file line with MAR bits settings:
Cache.setMarMeta(0x80000000, 0x20000000, Cache.PC | Cache.PCX | Cache.PFX | Cache.WTE);
What is wrong with my confiuration that example isn't working well after cache is turned on? What does it mean, that E_alreadyDefined: Hwi already defined: intr# 5? Something with IPC?
I've changed only platform file and added MAR bits settings in cfg file.
In cfg file, on the beginning of file, is also PlatformLib loaded. That was in qmssIpcBenchmark example file.
var PlatformLib = xdc.loadPackage('ti.platform.evmc6670l');
Maybe this is a problem? I don't know how to change in cfg file load defaut platform library to load new one C6670_with_DDR3.
In attachment are cfg file and new platform file.
Thanks.
Regards,
Lukasz.