Hello
I have encountered a specific interesting problem related with response times while using integrated comparator in MSP430g2553, and hope that some professional from the field could explain the origin of the problem or suggest some possible solution. Problem is a bit complicated so it will take some space to explain it.
My setup is following, I am using the integrated comparator as a simple repeater for some data transmission clock signal in my application. To form the repeater, I input signal in CA0 (P1.0) pin connected to “+” terminal, and use internal reference connected to “–“ terminal. CAOUT (P3.7) is used as output port. Actually in my application requires that I use multiple MSP430g2553 devices in cascade and the clock signal is repeated in every stage, so there are multiple repetitions of the same signal.
First thing I noticed was that the comparator tends to change the clock signal duty cycle – either by stretching or narrowing the positive pulse width, depending on comparator reference used. After few repetitions the clock signal gets really distorted, however, you can relatively quickly understand the source of the problem, when you look to real shape of the clock signal and think how the comparator works with different reference voltages. I was able to overcome the problem by introducing some sort of calibration algorithm that first measures the incoming clock positive pulse width and then decides which internal reference to use in order to maintain the clock signal duty cycle roughly around 50%.
The real problem which I can’t solve is a bit more strange and I can’t figure out the source of it. My clock signal pattern is following: I have series of 8 clock pulses (1 Mhz), and then some delay in between them. I noticed that in the repeated signal the very first edge of the 8 pulse pack is with longer delay than all other edges. This results in reduction of the period for the first clock pulse in each 8 clock pulse pack (all other following edges in the 8 pulse pack are repeated as expected). This difference is very small (just few ns) and normally might not even be noticed, however, as my application require a large number of repetitions, this small, consistent difference adds and in the end after some 20 repetitions, for each pack of 8 clock pulses, the first pulse width (and the period) have noticeably shrunk while at the same time rest of the pulses in 8 pulse pack are repeated as expected and maintain exactly the same period. In short – for each pack the first pulse is not repeated as the rest.
I did a bit further experiments with signal generator and wide band oscilloscope and to my surprise I found out that the comparator response time is somehow dependent on the input signal frequency. For example the response time for 100 kHz signal is few ns slower, than response time of 1 MHz signal. This somehow explains why the first edge after some steady signal period in my clock line could be repeated a bit slower than following edges, however, this feels really strange and counterintuitive.
Has anyone encountered this? Could this be related to properties of MSP430 integrated comparators, like power saving feature when comparator activity is lower, or it is a problem for all comparators in general?
Of course, solution would be either to lower clock signal frequency or use some external high speed comparator which would reduce the impact from this effect, however, my aim is to have as compact and low power hardware design as possible, while maintaining relatively fast data transfer. Also the 120ns rated response time for MSP430g2553 comparator_A+ in each repetition is acceptable for 1Mhz clock signal in my design, so there is actually no real need for "faster" comparator, if the problem of first pulse distortion is solved.
Thank you in advance,
Atis