Hi,
We have a custom board with the DM8148 CYE2 and we want to run the DDR3 @ 533 MHz.
As far as I get it from the datasheet DDR3 @ 533 MHz requires to run the core domain at OPP166, which in turn requires CVDD to be 1.35V.
As changing the DDR PLL cannot be done while the DDR is in use the setting of the DDR PLL for 533 MHz needs to be done in the early steps of U-Boot (stage1), before it is relocated to DDR memory.
The PMIC (TPS659113) runs CVDD at 1.2 V by default, but 1.35V is required for OPP166. This can be changed via I2C, but I2C for the DM814x cannot be used before U-Boot has been moved to DDR as the driver uses some global variables.
So this looks like a chicken and egg problem, to run the DDR @ 533 MHz we need to raise CVDD via I2C but to do that we need to be using the DDR, but then we cannot change the DDR PLL as DDR is in use.
How is this supposed to be done in U-Boot then? I could not find any indication of it in the DM81xx U-Boot user guide on the wiki.
I guess one could initialize the DDR PLL for 533 MHz regardless of CVDD being at 1.2V and then raise it to 1.35V as soon as U-Boot is relocated to DDR, but this does not seem very reliable as the datasheet says that for 533 MHz OPP166 is needed and for OPP166 CVDD must be 1.35V. It works on my test bench, but I would not be comfortable to do it on a product.