The 5xx/6xx user's guide (slau208k) and other discussion in this forum suggests that the best way to reliably read a timer counter when the timer clock is asynchronous to MCLK is to use a capture register and trigger the capture in code by toggling CCIS0 of the corresponding control register. The text description and example code from the user's guide is:
Captures can be initiated by software. The CMx bits can be set for captureon both edges. Software then sets CCIS1 = 1 and toggles bit CCIS0 to switchthe capture signal between VCC and GND, initiating a capture each time CCIS0 changes state:
MOV #CAP+SCS+CCIS1+CM_3,&TA0CCTL1 ; Setup TA0CCTL1, synch. capture mode, Event trigger on both edges of capture input.
XOR #CCIS0,&TA0CCTL1 ; TA0CCR1 = TA0R
This is incorrect because of the inclusion of SCS in the example TA0CCTL1 configuration.
Documentation says: Setting the SCS bit synchronizes the capture with the next timer clock.
Real-world (verified to my satisfaction with the MSP430F5438A) says: Setting the SCS bit synchronizes the capture with the next falling edge of the timer clock (slightly different). A capture will occur even if the input signal has returned to its original state before a clock transition occurred.
When SCS is set the CCR register is not loaded from TA0R until a falling edge is observed on the timer clock. If the timer clock is asynchronous to and slower than MCLK, the value of TA0CCR1 immediately after the XOR above will not necessarily be TA0R, nor is it true that a capture is initiated each time CCIS0 changes state.
I have only checked Timer_B on the MSP430F5438A, so other timer peripherals may behave differently.