Hi,
I'm debugging the DDR3 interface on a custom AM3874 design. It's pretty close to the Mistral DM8148 evaluation schematic, except I'm using a single 16-bit DDR3 chip (MT41J256M16HA-093) on each of the ARM's two interfaces. This chip is compatible with DDR1066, so I've bumped u-boot's PLL setup code to match the 533 Mhz clock. I've used the register configuration spreadsheet to modify my timing.
Running u-boot's "mtest" command gives the following output:
TI-MIN#mtest 0x80000000
Pattern 00000000 Writing... Reading...
Mem error @ 0x80000010: found 00000000, expected 00000004
Mem error @ 0x80000020: found 00000000, expected 00000008
Mem error @ 0x80000030: found 00000000, expected 0000000C
Mem error @ 0x80000040: found 00000000, expected 00000010
Mem error @ 0x80000050: found 00000000, expected 00000014
Mem error @ 0x80000060: found 00000000, expected 00000018
Mem error @ 0x80000070: found 00000000, expected 0000001C
Mem error @ 0x800000F0: found 0000002C, expected 0000003C
If I look at the memory afterwards using "md", I see
80000000: 00000000 00000001 00000002 00000003 ................
80000010: 00000000 00000005 00000006 00000007 ................
80000020: 00000000 00000009 0000000a 0000000b ................
80000030: 00000000 0000000d 0000000e 0000000f ................
80000040: 00000000 00000011 00000012 00000013 ................
80000050: 00000000 00000015 00000016 00000017 ................
80000060: 00000000 00000019 0000001a 0000001b ................
80000070: 00000000 0000001d 0000001e 0000001f ................
80000080: 00000020 00000021 00000022 00000023 ...!..."...#...
80000090: 00000024 00000025 00000026 00000027 $...%...&...'...
800000a0: 00000028 00000029 0000002a 0000002b (...)...*...+...
800000b0: 0000002c 0000002d 0000002e 0000002f ,...-......./...
800000c0: 00000030 00000031 00000032 00000033 0...1...2...3...
800000d0: 00000034 00000035 00000036 00000037 4...5...6...7...
800000e0: 00000020 00000039 0000003a 0000003b ...9...:...;...
800000f0: 0000003c 0000003d 0000003e 0000003f <...=...>...?...
It looks like the first few bits of every fourth word are corrupted (either during the write, or during the read.) I'm still looking through documentation and trying settings, but I'm hoping this looks obvious to someone here. Any hints?
My register settings are
#define DDR3_EMIF_SDRAM_CONFIG 0x61C25b32
#define DDR3_EMIF_TIM1 0x0ef146e4
#define DDR3_EMIF_TIM2 0x40408023
#define DDR3_EMIF_TIM3 0x51a008c0
#define DDR_EMIF_REF_CTRL 0x0000081e
#define DDR0_IO_CTRL_DEFINE 0x00030303
#define DDR1_IO_CTRL_DEFINE 0x00030303
#define DDR3_EMIF_SDRAM_ZQCR 0x500797cf
#define DDR3_EMIF_READ_LATENCY 0x00170209
thanks,
Graeme