Hi, I'm using a PCM1680 with a variable, non-standard sample rate. My digital audio processors require an input frequency of 144 times the sample rate and I want to use 512 times oversampling for the PCM1680. To achieve this I thought of using the CDCE913 programmable clock, it can output both frequencies and they are in sync.
I was looking at the datasheet for the PCM1680 and it shows a recommended layout, however the clock path is not shown. Do you have any advice on the layout of the CDCE913? Since it supplies the clock for both my digital section and the PCM1680 it is not strictly part of either of those sections. Wouldn't the split in the ground plane be bad for EMC if I lay out the clock lines to both sides? What return path should I provide for the 144xfs clock?
I've included an image of the recommended layout. My changes are in red. I also need an additional LDO to get the required voltages for the CDCE913.
