What will be the behavior in case DSP and EDMA3 controller both tries to access DDR at same time

Hi All , 

I am trying to understand what will happen if DSP and EDMA both generates request for DDR access at same time ..

Below mentioned is the details for the scenario i am referring:-

1. The EDMA3 is configured to continuously transfer data read from FPGA [connected by EMIF]  to section of DDR ...

2. DSP is continuously and simultaneously transferring the data received from EDMA to ARM processor.

3. There is no hand-shaking or any synchronization between DSP and EDMA3 controller

     [Like both are accessing same DDR in free run , independent of each other operation ]

4. As per my knowledge , as the destination is same for both the master [DSP & EDMA3] only one of them will get the

    acess to DDR due to default system arbitation

5. So let us say EDMA is dumping FPGA data to DDR .It has transmitted 100 Bytes out of 512 bytes to DDR2. 

     At this stage the EDMA transfer is not completed ,and there is an request of DDR data from DSP . 

    Since DSP has the higher priority over EDMA3 , the control to DDR will be transferred to DSP & hence DSP will start to fetch DDR data. 

Based on above mentioned scenario w.r.t EDMA controller :-

a] Will EDMA3 loose rights to use system resource instantaneously or will it complete the transfer ?

b] If it will complete the transfer before handing the system resource to DSP 

     Will it complete the transfer of ENTIRE DATA length of 512 bytes

     [It has transmitted 100 out of 512 bytes when the request from DSP was generated]

     or

     It will transmit the pending data after DSP has released the resources. 

c]  Once EDMA get back the resource :-

    Does EDMA3 maintains a record as to how much data was transferred to DDR so that he starts 

    from 101 data till 512.

    or 

    EDMA3 will start from 0-512 again ??

The reason for this is because we have DSP and EDMA3 both accessing same section of DDR without any hand-shaking or synchronization 

among them .

Individually EDMA3  and DSP both logic is tested and works without any DATA corruption. 

But when above mention scenario happens i get DATA_CORRUPTION..

Thank You,

Ashish Mishra 

[Banglore/ India]