Hi I wish to make a connection between 6670 DSP (with respect to each of 4 cores) and FPGA (supporting SERDES link and CPRI protocol).
The operartions to be implemented are read and write.
In my case, previously SRIO was used for this interface but now SRIO is to be used for inter DSP communication. Hence SRIO cannot be used.
I am left with option of using AIF2 peripheral, but unable to decide on which feature/mode I can use for my use case.
After going through the available literature and sample code on AIF2, I believe generic packet mode for CPRI is the most suitable option.
But, I wish to use it for 1.4MHz LTE Rate and see that there is a specific option available in AIF2. But, I am not sure if I can use LTE mode for inter device communication. Can anyone please suggest if LTE mode can be used in my scenario?
Also, please suggest on what basis can I select a core for transmission/reception of messages? (IN SRIO, I was able to distinguish the core number with the help of LSU registers)
Is there any sample/reference code available for the DSP-FPGA communication using LTE feature for AIF2?
Is there any sample/reference material (other than User guide and LLD) available for the same?
Also, please suggest what components of AIF2 are covered by loopback mode supported by AIF2? (For SRIO, we had Digital and SERDES loopback modes, but for AIF2, I read only internal loopback mode is available. So, wish to know how it maps to loopback modes available in SRIO?)
In anticipation of response for all/some of the above queries
Thanks
Regards
Anuj Agarwal