Part Number:ADC12D1000
Hi,
I'm wondering whether the test pattern shown in table 3 of the adc12d1000 datasheet for the non-demux mode is correct.
Indeed I'm trying to synchronize my FPGA with the ADC operated at 1GHz (DCLK frequency hence is 1/2*fadc=500MHz) and I observe the following sequence for the I bus :
T0 : 004h
T1 : 004h
T2 : FFBh
T3 : FFBh
T4 : 004h
T5 : 004h
T6 : FFBh
T7 : FFBh
T8 : 004h
T9 : 004h
I'm sure that the data are sampled correctly at the FPGA input, because I perform a data phase alignment.
And I can guarantee that the data are sampled in the middle of the window.
Moreover if I compare the data I'm observing with the pattern shown in table 2 for the demux mode for the Id output,
it seems consistent with what I observe considering each sample is recorded twice.
I assume the pattern generator is located before the 1:2 demuxer, and that it is merely the same.
Thus it would make sense to see each sample of table 2 twice in the stream if the demux is not activated.
Can you confirm my observation, and if true correct the datasheet?
Thanks in advance, best regards