DAC37J82: JESD start match character config79

Part Number:DAC37J82

Config register 79 has a JESD character match field that determines when to start buffering. Can it be used to align the JESD samples from the sender (FPGA) with the DACs across multiple modules. That is, in the absence of SYSREF and subclass 1, can it perform a similar function? Can I get more details on this register?

Thanks