issues in GPMC interfacing of FPGA DDR3

Hi,

We are using DM814x processor and FPGA in our custom board. A 2Gb DDR3 is  connected to FPGA. We should interface with DDR3 using GPMC connected to FPGA. I've written FPGA driver for I2C and SPI communication between processor and FPGA (for FPGA control register access only) and also to access that FPGA DDR3 using GPMC.  Here is the piece of code that I've written.

err = i2c_add_driver (&i2c_fpga_driver);
if (err != 0) {
printk(KERN_ERR "i2c_add_driver failed\n");
return err;
}

err = spi_register_driver(&spi_fpga_driver);
if (err != 0) {
printk(KERN_ERR "spi_register_driver failed\n");
return err;
}

printk(KERN_DEBUG "Getting Chip Select\n");

if (gpmc_cs_request(GPMC_CHIP_SEL_NUM, SZ_256M, &fpga_i2c_di->control_mem_base) < 0) {
printk(KERN_DEBUG "%d: %s in %s\n", __LINE__, __func__, __FILE__);
printk(KERN_ERR "gpmc_cs_request: fail\n");
goto free;
}
printk(KERN_DEBUG "Got CS1, address = %lx\n",  fpga_i2c_di->control_mem_base);

if (!request_mem_region(fpga_i2c_di->control_mem_base, SZ_256M, "fpga_cs")) {
printk(KERN_DEBUG "%d: %s in %s\n", __LINE__, __func__, __FILE__);
printk(KERN_ERR "Request_mem_region failed.\n");
gpmc_cs_free(GPMC_CHIP_SEL_NUM);
goto free;
}

fpga_i2c_di->ctl_addr = ioremap_nocache(fpga_i2c_di->control_mem_base, SZ_256M);

printk(KERN_DEBUG "After Chipselect & remap.\n");
printk(KERN_DEBUG "Config1: 0x%x\n", gpmc_cs_read_reg(GPMC_CHIP_SEL_NUM, GPMC_CS_CONFIG1));
printk(KERN_DEBUG "Config2: 0x%x\n", gpmc_cs_read_reg(GPMC_CHIP_SEL_NUM, GPMC_CS_CONFIG2));
printk(KERN_DEBUG "Config3: 0x%x\n", gpmc_cs_read_reg(GPMC_CHIP_SEL_NUM, GPMC_CS_CONFIG3));
printk(KERN_DEBUG "Config4: 0x%x\n", gpmc_cs_read_reg(GPMC_CHIP_SEL_NUM, GPMC_CS_CONFIG4));
printk(KERN_DEBUG "Config5: 0x%x\n", gpmc_cs_read_reg(GPMC_CHIP_SEL_NUM, GPMC_CS_CONFIG5));
printk(KERN_DEBUG "Config6: 0x%x\n", gpmc_cs_read_reg(GPMC_CHIP_SEL_NUM, GPMC_CS_CONFIG6));
printk(KERN_DEBUG "Config7: 0x%x\n", gpmc_cs_read_reg(GPMC_CHIP_SEL_NUM, GPMC_CS_CONFIG7));
printk(KERN_DEBUG "\nRemap, address = 0x%x\n",  (unsigned int) fpga_i2c_di->ctl_addr);

When I execute the above driver code, 

physical addr returned by gpmc_cs_request (fpga_i2c_di->control_mem_base) = 0x10000000

virtual addr returned by ioremap_nocache function(fpga_i2c_di->ctl_addr) = 0xdc000000

We are using address and data multiplexed interfacing of NOR protocol. So, 27 lines are connected to DDR3 to access 256MB (each memory location is of 2 bytes). The problem is, while making read and write transactions using the virtual address returned from ioremap, physical address received on bus 0x4000000.  But I expect the address 0x0000000  on the bus. What is the mistake in this code?? how is this possible?? Can anyone please help in this issue?? 

Also we use only two chip selects in our board. NAND uses only 16MB which is not colliding with this ddr3 address.