Using TI calls to set/reset a pin versus use a struct

Part Number:TMS320C6748

Tool/software: TI C/C++ Compiler

I have seen a strange behavior I somply don't understand:

I have worked with the Delfino controllers and really enjoyed the struct mechanism to access registers and bits within the peripherals and I thought I would try the same for 6748 DSP.

So I made a header file with structs to define the GPIO registers and bits based on the way it is done for the 2000 series. See file.

Also I made a little test file to see how it works. See file.

And now comes the strange stuff:
When I single step the     "GPIOPinWrite( SOC_GPIO_0_REGS, GPIO_PIN_NUMBER(6,6), 1 );" and the "GpioBanks.B6_7.SET.bit.SETA6 = 1;" lines, I got two very different results when counting the clock pulses in Timer 2.

For the TI call (GPIOPinWrite) the number of clock pulses are around 25 to 30 and when I test the struct the number of pulses is 3 to 5. Looks like a huge improvement: 5 times faster when using the struct way.

Great, let's try it in real time without the debugger: Now it turns out the TI call is faster (~40%?) than the struct way. Bummer. I looked at the actual pin, GPIO 6,6, on a  scope.

But how come it seems faster when using the debugger as compared to the free run?

Any good explanation?

Thanks,

Claus Knudsen

//CODE


/*
 * main.c
 */

#include "psc.h"

#include "soc_C6748.h"
#include "gpio.h"
#include "pll_regs.h"
#include "timer.h"

#include "C6000GPIOStruct.h"

#define GPIO_PIN_NUMBER(BANK,PINNR) (BANK * 16 + PINNR + 1)

void TestGPIO_STRUCT (void);
void ConfigandStartTimer_2( void );



int main(void) {
	
    PSCModuleControl(SOC_PSC_1_REGS, HW_PSC_GPIO, PSC_POWERDOMAIN_ALWAYS_ON,
           PSC_MDCTL_NEXT_ENABLE);

    PINMUX14 = 0x00000080;      // set pin to GPIO(6,6)

    GPIODirModeSet( SOC_GPIO_0_REGS, GPIO_PIN_NUMBER(6,6), GPIO_DIR_OUTPUT );

    ConfigandStartTimer_2();

    while (1)
	{
	    TestGPIO_STRUCT();
	}
}



#pragma DATA_SECTION(GpioBanks , "GPIO_REG");
volatile struct GPIO_BANKS_0_8 GpioBanks;


void TestGPIO_STRUCT (void)
{

    GPIOPinWrite( SOC_GPIO_0_REGS, GPIO_PIN_NUMBER(6,6), 1 ); // step
    GPIOPinWrite( SOC_GPIO_0_REGS, GPIO_PIN_NUMBER(6,6), 0 ); // step


    // Use the struct two times in order to distinguish between the TI call and the struct
    GpioBanks.B6_7.SET.bit.SETA6 = 1;
    GpioBanks.B6_7.CLR.bit.CLRA6 = 1;
    GpioBanks.B6_7.SET.bit.SETA6 = 1;
    GpioBanks.B6_7.CLR.bit.CLRA6 = 1;


}


void ConfigandStartTimer_2( void )
{
    TimerConfigure( SOC_TMR_2_REGS, TMR_CFG_64BIT_CLK_INT);

    TimerPeriodSet( SOC_TMR_2_REGS, TMR_TIMER12, 0xFFFFFFFF );
    TimerPeriodSet( SOC_TMR_2_REGS, TMR_TIMER34, 0xFFFFFFFF );

    TimerEnable( SOC_TMR_2_REGS, TMR_TIMER12, TMR_ENABLE_CONT);
}


// Linker CMD file

// ============================================================================
// Linker Command File for Linking c674 DSP Programs
//
// These linker options are for command line linking only. For IDE linking,
// you should set your linker options in Project Properties.
//         -c                    Link Using C Conventions
//        -stack     0x1000        Software Stack Size
//        -heap    0x1000        Heap Area Size
// ===========================================================================
-stack 0x3000
//-heap 0x2000

// ============================================================================
//                         Specify the System Memory Map
// ============================================================================
MEMORY
{
    L1P:        o = 0x11E00000          l = 0x00008000
    L1D:        o = 0x11F00000          l = 0x00008000
    L2:         o = 0x11800000          l = 0x00040000
    SHARED_RAM: o = 0xC0000000          l = 0x00100000
    DDR2:       o = 0xC0100000          l = 0x07F00000
    EMIFA2      o = 0x60000000          l = 0x02000000
    GPIOMEM     o = 0x01E26010          l = 0xC8
}

// ============================================================================
//                 Specify the Sections Allocation into Memory
// ============================================================================
SECTIONS
{


    .cinit        >        L2               // Initialization Tables
    .pinit        >        SHARED_RAM//DDR2
    .init_array   >        L2               //
    .binit        >        L2               // Boot Tables
    .const        >        SHARED_RAM       //DDR2//L2               // Constant Data. was L2, now DDR2 with fpga code
    .switch       >        L2               // Jump Tables
    .text         >       L2// DDR2               // Executable Code
    .text:_c_int00: align=1024 > L2         // Entrypoint
    


    GROUP (NEARDP_DATA)                       // group near data
    {
       .neardata
       .rodata
       .bss                                   // note: removed fill = 0
    }             >        L2
    .far: fill = 0x0, load > L2             // Far Global & Static Variables
    .fardata      >        L2               // Was L2. Far RW Data
    .stack        >        L2               // Software System Stack
    .sysmem       >        L2               // Dynamic Memory Allocation Area
    .heap         >        DDR2
    {
      . += 0x01000000;
    }
    .cio          >        L2               // C I/O Buffer
    .vecs         >        L2               // Interrupt Vectors

    FPGASection   >        EMIFA2
    DDR2Funcs     >        DDR2
    SharedRAMFuncs >       SHARED_RAM
    LEVEL2        >        L2
    FASTMEM: fill = 0x0      >         L1D
    FASTPROG > L1P
    GPIO_REG > GPIOMEM
}

// Struct
/*
 * C6000GPIOStruct.h
 *
 *  Created on: Jan 10, 2017
 *      Author: claus
 */

#ifndef C6000GPIOSTRUCT_H_
#define C6000GPIOSTRUCT_H_
#include "cwk_types.h"


struct GPIO_DIR_BITS {
    uint32 DIRA0:1;
    uint32 DIRA1:1;
    uint32 DIRA2:1;
    uint32 DIRA3:1;
    uint32 DIRA4:1;
    uint32 DIRA5:1;
    uint32 DIRA6:1;
    uint32 DIRA7:1;
    uint32 DIRA8:1;
    uint32 DIRA9:1;
    uint32 DIRA10:1;
    uint32 DIRA11:1;
    uint32 DIRA12:1;
    uint32 DIRA13:1;
    uint32 DIRA14:1;
    uint32 DIRA15:1;

    uint32 DIRB0:1;
    uint32 DIRB1:1;
    uint32 DIRB2:1;
    uint32 DIRB3:1;
    uint32 DIRB4:1;
    uint32 DIRB5:1;
    uint32 DIRB6:1;
    uint32 DIRB7:1;
    uint32 DIRB8:1;
    uint32 DIRB9:1;
    uint32 DIRB10:1;
    uint32 DIRB11:1;
    uint32 DIRB12:1;
    uint32 DIRB13:1;
    uint32 DIRB14:1;
    uint32 DIRB15:1;

};

struct GPIO_OUT_BITS{
    uint32 OUTA0:1;
    uint32 OUTA1:1;
    uint32 OUTA2:1;
    uint32 OUTA3:1;
    uint32 OUTA4:1;
    uint32 OUTA5:1;
    uint32 OUTA6:1;
    uint32 OUTA7:1;
    uint32 OUTA8:1;
    uint32 OUTA9:1;
    uint32 OUTA10:1;
    uint32 OUTA11:1;
    uint32 OUTA12:1;
    uint32 OUTA13:1;
    uint32 OUTA14:1;
    uint32 OUTA15:1;

    uint32 OUTB0:1;
    uint32 OUTB1:1;
    uint32 OUTB2:1;
    uint32 OUTB3:1;
    uint32 OUTB4:1;
    uint32 OUTB5:1;
    uint32 OUTB6:1;
    uint32 OUTB7:1;
    uint32 OUTB8:1;
    uint32 OUTB9:1;
    uint32 OUTB10:1;
    uint32 OUTB11:1;
    uint32 OUTB12:1;
    uint32 OUTB13:1;
    uint32 OUTB14:1;
    uint32 OUTB15:1;

};


struct GPIO_SET_BITS{
    uint32 SETA0:1;
    uint32 SETA1:1;
    uint32 SETA2:1;
    uint32 SETA3:1;
    uint32 SETA4:1;
    uint32 SETA5:1;
    uint32 SETA6:1;
    uint32 SETA7:1;
    uint32 SETA8:1;
    uint32 SETA9:1;
    uint32 SETA10:1;
    uint32 SETA11:1;
    uint32 SETA12:1;
    uint32 SETA13:1;
    uint32 SETA14:1;
    uint32 SETA15:1;

    uint32 SETB0:1;
    uint32 SETB1:1;
    uint32 SETB2:1;
    uint32 SETB3:1;
    uint32 SETB4:1;
    uint32 SETB5:1;
    uint32 SETB6:1;
    uint32 SETB7:1;
    uint32 SETB8:1;
    uint32 SETB9:1;
    uint32 SETB10:1;
    uint32 SETB11:1;
    uint32 SETB12:1;
    uint32 SETB13:1;
    uint32 SETB14:1;
    uint32 SETB15:1;

};


struct GPIO_CLR_BITS{
    uint32 CLRA0:1;
    uint32 CLRA1:1;
    uint32 CLRA2:1;
    uint32 CLRA3:1;
    uint32 CLRA4:1;
    uint32 CLRA5:1;
    uint32 CLRA6:1;
    uint32 CLRA7:1;
    uint32 CLRA8:1;
    uint32 CLRA9:1;
    uint32 CLRA10:1;
    uint32 CLRA11:1;
    uint32 CLRA12:1;
    uint32 CLRA13:1;
    uint32 CLRA14:1;
    uint32 CLRA15:1;

    uint32 CLRB0:1;
    uint32 CLRB1:1;
    uint32 CLRB2:1;
    uint32 CLRB3:1;
    uint32 CLRB4:1;
    uint32 CLRB5:1;
    uint32 CLRB6:1;
    uint32 CLRB7:1;
    uint32 CLRB8:1;
    uint32 CLRB9:1;
    uint32 CLRB10:1;
    uint32 CLRB11:1;
    uint32 CLRB12:1;
    uint32 CLRB13:1;
    uint32 CLRB14:1;
    uint32 CLRB15:1;

};


struct GPIO_IN_BITS{
    uint32 INA0:1;
    uint32 INA1:1;
    uint32 INA2:1;
    uint32 INA3:1;
    uint32 INA4:1;
    uint32 INA5:1;
    uint32 INA6:1;
    uint32 INA7:1;
    uint32 INA8:1;
    uint32 INA9:1;
    uint32 INA10:1;
    uint32 INA11:1;
    uint32 INA12:1;
    uint32 INA13:1;
    uint32 INA14:1;
    uint32 INA15:1;

    uint32 INB0:1;
    uint32 INB1:1;
    uint32 INB2:1;
    uint32 INB3:1;
    uint32 INB4:1;
    uint32 INB5:1;
    uint32 INB6:1;
    uint32 INB7:1;
    uint32 INB8:1;
    uint32 INB9:1;
    uint32 INB10:1;
    uint32 INB11:1;
    uint32 INB12:1;
    uint32 INB13:1;
    uint32 INB14:1;
    uint32 INB15:1;

};


struct GPIO_SET_RIS_TRIG_BITS{
    uint32 SET_RIS_TRIGA0:1;
    uint32 SET_RIS_TRIGA1:1;
    uint32 SET_RIS_TRIGA2:1;
    uint32 SET_RIS_TRIGA3:1;
    uint32 SET_RIS_TRIGA4:1;
    uint32 SET_RIS_TRIGA5:1;
    uint32 SET_RIS_TRIGA6:1;
    uint32 SET_RIS_TRIGA7:1;
    uint32 SET_RIS_TRIGA8:1;
    uint32 SET_RIS_TRIGA9:1;
    uint32 SET_RIS_TRIGA10:1;
    uint32 SET_RIS_TRIGA11:1;
    uint32 SET_RIS_TRIGA12:1;
    uint32 SET_RIS_TRIGA13:1;
    uint32 SET_RIS_TRIGA14:1;
    uint32 SET_RIS_TRIGA15:1;

    uint32 SET_RIS_TRIGB0:1;
    uint32 SET_RIS_TRIGB1:1;
    uint32 SET_RIS_TRIGB2:1;
    uint32 SET_RIS_TRIGB3:1;
    uint32 SET_RIS_TRIGB4:1;
    uint32 SET_RIS_TRIGB5:1;
    uint32 SET_RIS_TRIGB6:1;
    uint32 SET_RIS_TRIGB7:1;
    uint32 SET_RIS_TRIGB8:1;
    uint32 SET_RIS_TRIGB9:1;
    uint32 SET_RIS_TRIGB10:1;
    uint32 SET_RIS_TRIGB11:1;
    uint32 SET_RIS_TRIGB12:1;
    uint32 SET_RIS_TRIGB13:1;
    uint32 SET_RIS_TRIGB14:1;
    uint32 SET_RIS_TRIGB15:1;

};


struct GPIO_CLR_RIS_TRIG_BITS{
    uint32 CLR_RIS_TRIGA0:1;
    uint32 CLR_RIS_TRIGA1:1;
    uint32 CLR_RIS_TRIGA2:1;
    uint32 CLR_RIS_TRIGA3:1;
    uint32 CLR_RIS_TRIGA4:1;
    uint32 CLR_RIS_TRIGA5:1;
    uint32 CLR_RIS_TRIGA6:1;
    uint32 CLR_RIS_TRIGA7:1;
    uint32 CLR_RIS_TRIGA8:1;
    uint32 CLR_RIS_TRIGA9:1;
    uint32 CLR_RIS_TRIGA10:1;
    uint32 CLR_RIS_TRIGA11:1;
    uint32 CLR_RIS_TRIGA12:1;
    uint32 CLR_RIS_TRIGA13:1;
    uint32 CLR_RIS_TRIGA14:1;
    uint32 CLR_RIS_TRIGA15:1;

    uint32 CLR_RIS_TRIGB0:1;
    uint32 CLR_RIS_TRIGB1:1;
    uint32 CLR_RIS_TRIGB2:1;
    uint32 CLR_RIS_TRIGB3:1;
    uint32 CLR_RIS_TRIGB4:1;
    uint32 CLR_RIS_TRIGB5:1;
    uint32 CLR_RIS_TRIGB6:1;
    uint32 CLR_RIS_TRIGB7:1;
    uint32 CLR_RIS_TRIGB8:1;
    uint32 CLR_RIS_TRIGB9:1;
    uint32 CLR_RIS_TRIGB10:1;
    uint32 CLR_RIS_TRIGB11:1;
    uint32 CLR_RIS_TRIGB12:1;
    uint32 CLR_RIS_TRIGB13:1;
    uint32 CLR_RIS_TRIGB14:1;
    uint32 CLR_RIS_TRIGB15:1;

};

struct GPIO_SET_FAL_TRIG_BITS{
    uint32 SET_FAL_TRIGA0:1;
    uint32 SET_FAL_TRIGA1:1;
    uint32 SET_FAL_TRIGA2:1;
    uint32 SET_FAL_TRIGA3:1;
    uint32 SET_FAL_TRIGA4:1;
    uint32 SET_FAL_TRIGA5:1;
    uint32 SET_FAL_TRIGA6:1;
    uint32 SET_FAL_TRIGA7:1;
    uint32 SET_FAL_TRIGA8:1;
    uint32 SET_FAL_TRIGA9:1;
    uint32 SET_FAL_TRIGA10:1;
    uint32 SET_FAL_TRIGA11:1;
    uint32 SET_FAL_TRIGA12:1;
    uint32 SET_FAL_TRIGA13:1;
    uint32 SET_FAL_TRIGA14:1;
    uint32 SET_FAL_TRIGA15:1;

    uint32 SET_FAL_TRIGB0:1;
    uint32 SET_FAL_TRIGB1:1;
    uint32 SET_FAL_TRIGB2:1;
    uint32 SET_FAL_TRIGB3:1;
    uint32 SET_FAL_TRIGB4:1;
    uint32 SET_FAL_TRIGB5:1;
    uint32 SET_FAL_TRIGB6:1;
    uint32 SET_FAL_TRIGB7:1;
    uint32 SET_FAL_TRIGB8:1;
    uint32 SET_FAL_TRIGB9:1;
    uint32 SET_FAL_TRIGB10:1;
    uint32 SET_FAL_TRIGB11:1;
    uint32 SET_FAL_TRIGB12:1;
    uint32 SET_FAL_TRIGB13:1;
    uint32 SET_FAL_TRIGB14:1;
    uint32 SET_FAL_TRIGB15:1;

};


struct GPIO_CLR_FAL_TRIG_BITS{
    uint32 CLR_FAL_TRIGA0:1;
    uint32 CLR_FAL_TRIGA1:1;
    uint32 CLR_FAL_TRIGA2:1;
    uint32 CLR_FAL_TRIGA3:1;
    uint32 CLR_FAL_TRIGA4:1;
    uint32 CLR_FAL_TRIGA5:1;
    uint32 CLR_FAL_TRIGA6:1;
    uint32 CLR_FAL_TRIGA7:1;
    uint32 CLR_FAL_TRIGA8:1;
    uint32 CLR_FAL_TRIGA9:1;
    uint32 CLR_FAL_TRIGA10:1;
    uint32 CLR_FAL_TRIGA11:1;
    uint32 CLR_FAL_TRIGA12:1;
    uint32 CLR_FAL_TRIGA13:1;
    uint32 CLR_FAL_TRIGA14:1;
    uint32 CLR_FAL_TRIGA15:1;

    uint32 CLR_FAL_TRIGB0:1;
    uint32 CLR_FAL_TRIGB1:1;
    uint32 CLR_FAL_TRIGB2:1;
    uint32 CLR_FAL_TRIGB3:1;
    uint32 CLR_FAL_TRIGB4:1;
    uint32 CLR_FAL_TRIGB5:1;
    uint32 CLR_FAL_TRIGB6:1;
    uint32 CLR_FAL_TRIGB7:1;
    uint32 CLR_FAL_TRIGB8:1;
    uint32 CLR_FAL_TRIGB9:1;
    uint32 CLR_FAL_TRIGB10:1;
    uint32 CLR_FAL_TRIGB11:1;
    uint32 CLR_FAL_TRIGB12:1;
    uint32 CLR_FAL_TRIGB13:1;
    uint32 CLR_FAL_TRIGB14:1;
    uint32 CLR_FAL_TRIGB15:1;

};

struct GPIO_INTSTAT_BITS{
    uint32 INTSTATA0:1;
    uint32 INTSTATA1:1;
    uint32 INTSTATA2:1;
    uint32 INTSTATA3:1;
    uint32 INTSTATA4:1;
    uint32 INTSTATA5:1;
    uint32 INTSTATA6:1;
    uint32 INTSTATA7:1;
    uint32 INTSTATA8:1;
    uint32 INTSTATA9:1;
    uint32 INTSTATA10:1;
    uint32 INTSTATA11:1;
    uint32 INTSTATA12:1;
    uint32 INTSTATA13:1;
    uint32 INTSTATA14:1;
    uint32 INTSTATA15:1;

    uint32 INTSTATB0:1;
    uint32 INTSTATB1:1;
    uint32 INTSTATB2:1;
    uint32 INTSTATB3:1;
    uint32 INTSTATB4:1;
    uint32 INTSTATB5:1;
    uint32 INTSTATB6:1;
    uint32 INTSTATB7:1;
    uint32 INTSTATB8:1;
    uint32 INTSTATB9:1;
    uint32 INTSTATB10:1;
    uint32 INTSTATB11:1;
    uint32 INTSTATB12:1;
    uint32 INTSTATB13:1;
    uint32 INTSTATB14:1;
    uint32 INTSTATB15:1;

};

union GPIO_DIR_REG{
    uint32      all;
    struct      GPIO_DIR_BITS bit;
};

union GPIO_OUT_REG{
    uint32      all;
    struct      GPIO_OUT_BITS bit;
};

union GPIO_SET_REG{
    uint32      all;
    struct      GPIO_SET_BITS bit;
};

union GPIO_CLR_REG{
    uint32      all;
    struct      GPIO_CLR_BITS bit;
};

union GPIO_IN_REG{
    uint32      all;
    struct      GPIO_IN_BITS bit;
};

union GPIO_SET_RIS_TRIG_REG{
    uint32      all;
    struct      GPIO_SET_RIS_TRIG_BITS bit;
};



union GPIO_CLR_RIS_TRIG_REG{
    uint32      all;
    struct      GPIO_CLR_RIS_TRIG_BITS bit;
};

union GPIO_SET_FAL_TRIG_REG{
    uint32      all;
    struct      GPIO_SET_FAL_TRIG_BITS bit;
};

union GPIO_CLR_FAL_TRIG_REG{
    uint32      all;
    struct      GPIO_CLR_FAL_TRIG_BITS bit;
};

union GPIO_INTSTAT_REG{
    uint32      all;
    struct      GPIO_INTSTAT_BITS bit;
};

struct GPIO_BANK{
    union GPIO_DIR_REG DIR;
    union GPIO_OUT_REG OUT;
    union GPIO_SET_REG SET;
    union GPIO_CLR_REG CLR;
    union GPIO_IN_REG  IN;
    union GPIO_SET_RIS_TRIG_REG SET_RIS;
    union GPIO_CLR_RIS_TRIG_REG CLR_RIS;
    union GPIO_SET_FAL_TRIG_REG SET_FAL;
    union GPIO_CLR_FAL_TRIG_REG CLR_FAL;
    union GPIO_INTSTAT_REG INTSTAT;
};

struct GPIO_BANKS_0_8{
    struct GPIO_BANK B0_1;
    struct GPIO_BANK B2_3;
    struct GPIO_BANK B4_5;
    struct GPIO_BANK B6_7;
    struct GPIO_BANK B8;
};


#endif /* C6000GPIOSTRUCT_H_ */