DAC34SH84EVM: FIFO enabling creates spike transitions+ channel swapping

Part Number:DAC34SH84EVM

Hi,

we are using a DAC34SH84EVM in order to generate constant output levels that change every 200us. We provide  data and CLK through the FMC adapter connected to a SPARTAN FPGA. We managed to make it work pretty fine with the FIFO disabled as shown in screenshot. However, when resetting multiple times the channels are swapping between each other.

As a result we thought to try and enable the FIFO in order to properly lock the DATA to each channel. However, we see that the transition from one level to the other comes with a short period of unwanted spikes, probably due to poor locking. Moreover, the arbitrary swapping of channels is still present.

Any ideas on how to proceed?

Thanks,

Christos