TMS320F28375D: bit reversed addressing and Q15 format for vcuII fft usage

Part Number:TMS320F28375D

Dear TI,

     Using spruhs1a and c28x-vcu-lib-ug.pdf it's not 100% clear.

     In the code comments I see reference to the the data buffers needing to be in Q15 format, and I see reference to bit reversed addressing.

I infer the following:

-  we must align the memory of the input buffer as per the 2x the size of the CFFT function chosen

- we don't explicit need to rearrange our data, or call a function to rearrange our data (if we are using the VCUII)  prior to calling the chosen FFT function (complex FFT in my case), the bit reversed addressing is 'built into' the addressing mode which is why the special alignment above is necessary for it to work.  ie: bit reversed addressing is 'hidden' to the caller of the function as long as the buffer is aligned as above.

-  I infer I MUST scale my data to Q15 format, so my complex number is +-1.0 +/- I*1.0 maximum...  represented in Q15 format,

Thanks for confirming if I'm reading the above correctly from the documentation.