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AM3356: DDR2 bus termination on controller side

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Part Number:AM3356

Question from field:

Customer is using DDR2 and facing memory read errors, usually same bits (are read as 1).

The solution implemented was adding pull downs on all pins in ddr_xxx_IOCtl registers.

Questions

a) doing some research in our documentation, it was found that these pull-downs should be activated only when the bus is in idle state. Correct?

b) are there termination resistors at the AM335x side during memory read cycle?

c) bottom line is what is the logic behind the solution implemented above that fixed the memory read issues?


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