Part Number:AM5726
Dear All,
we have a monochrome image sensor connected to an FPGA which converts the pixel data from serial to parallel. The pixel data is then transferred to VIN1A of an AM5726.
The pixels are not read out and transferred in the normal order by the image sensor so that I need to sort them in the processor.
Each line of the image is divided into kernels and each kernel consists of 8 pixels:
Line x: ...... | kernel N-1 | kernel N | kernel N+1|........
Then within even kernels the pixel order is 0, 2, 4, 6, 1, 3, 5, 7 and
within odd kernels the order is 7, 5, 3, 1, 6, 4, 2, 0
My question is if this pixel sorting is possible with the DMA-Hardware of the AM5726 (VPDMA or a combination of VPDMA and EDMA3) without having two times the delay of a DMA transfer. Would it perhaps be possible to trigger an EDMA3 transfer for the pixel sorting after every two kernels having been transferred to internal memory by VPDMA? Since I only need to transfer monochrome or raw image data to memory and I do not need most of the features of the VIP would it be possible to only use only EDMA3 for the transfer?
Is there source code or examples available for such a configuration of the DMA engines in addition to the Linux SDK and the EVM?
Thanks for your support.
Best regards,
Stephan