Hello,
I have own board closely matching recommended design with LMK04906 as per DS, the chip works well
except a few problems.
1/ LOS detector on CLKIN1 is weird. CLKIN1 is N with 100n to GND, P - 50R to gnd and 100n to SMA conn.
Configured as bipolar input, hard selected CLKIN_SELECT_MODE=1, I connected 48MHz clock to input.
PLL1/2 locks correcly but when I output LOS on status_clkin1 pin, it only goes to 1 for about 0.2sec when
I stop external clock. Then LOS goes back to 0. I suspected noise thus I configured HOLDOVER_STATUS to
output PLL1 R/2 - I correcly see divided clock which disappear once I stop 48M clock. But LOS doesn't detect it.
LOS_TIMEOUT=0, LOS_EN=1. Interestingly LOS on CLKIN2 works.... CLKIN0 is unconnected..
2/ SYNC_EN_AUTO works only with SYNC_QUAL. When I set SYNC_EN_AUTO=1 and write to R0 (yes I use
3 xtra clock with LE=1) all clock outputs set to sync goes LOW forever. Like if SYNC is asserted but not deasserted.
When I add SYNC_QUAL (and set feedback mux) then it starts to work. It seems like if auto sync doesn't work
for non qualified syncing. Is it the case (missing in DS) or my fault ?
3/ in FIXED delay mode, I used SYNC_POL_INV, to sync after R0 update. One clock is connected as ADC clk
other to ADC's input. The intention was to measure LMK's jitter. Interestingly I found that sometimes when
I program dig. delay it behaves as if different one was programmed. Usually by 2 steps. I suspected programing
error but when I enabled DYNAMIC DELAY it started to work.
Any idea how to resolve the problem ? Maybe I can use mux to feed clkout3,4 from oscin at 40MHz thus I can
see delay on my scope (sub ns delay is rather hard to see for me), but will SYNCing work when I don't use
main clock distribution tree ?
thanks, Martin