2 issues, both are transient related and have show up during product testing.
1) Please confirm that the limit for voltage between SOURCE and RTN is 100V for the absolute maximum. The datasheet specifies this for the SENSE pin which is connected through a low value resistor (0.01 ohm in the application schematic) so SOURCE should track very close to SENSE.
2) The problem that we are seeing is that when we apply a Common Mode transient to the frame ground of our product, we see greater than -100V between SOURCE and RTN (as much as -110V). This transient is coupled through D1 (from application drawing on page 1 of datasheet) which is actually reversed biased during the transient. The reverse biased current through D1 is on the order of 250uA (1pF X 500V/2uS = 250uA). This current pulls the voltage between RTN to SOURCE from a nominal -50V down to -110V which exceeds the TPS2350 absolute maximum ratings. We think a simple solution to this problem may be to place a .01uF capacitor between SOURCE and RTN. The capacitor divider between the 1000pF cap and the ~1pF reversed biased capacitance of D1 should reduce the coupled transient to virtually nothing.
We need to know if this is a valid solution or if a better one can be proposed.