CCS/TMS320F28379D: CCS/F28379D

Part Number: TMS320F28379D

Tool/software: Code Composer Studio

  Hi Nima,
I generated XOR of three PWM signals. Now I need to use this XOR'ed signal as PWM for Phase A. I need to set this signal as master and generate PWMs for phase B and C as slave (which are 120 and 240 degrees) phase shifted from phase A). Can you please suggest me how to do it?

My code is attached below. Here I am XOR-ing signals A1, A2 and A3. XOR'ed signal is A which I need to use as PWM for phase A. Then I need to use it as master PWM (PWM 3) and use PWM 4 and 5 as slave PWMs for Phase B and C respectively. This code does not give me any output at PWM 3. I can see the XOR'ed output at GPIO 14 but I do not see anything at GPIO 4 (PWM 3).

Please suggest me how to use an internally generated signal as a PWM signal and use it to generate 2 other phase shifted PWMs.

    A1 = GpioDataRegs.GPADAT.bit.GPIO20;
    A2 = GpioDataRegs.GPADAT.bit.GPIO22;
    A3 = GpioDataRegs.GPADAT.bit.GPIO16;

    A1_NOT = 1 - A1;
    A2_NOT = 1 - A2;
    A3_NOT = 1 - A3;

    A = ((A1+A2+A3) * (A1_NOT+A2_NOT+A3) * (A1_NOT+A2+A3_NOT) * (A1+A2_NOT+A3_NOT));  //XOR of signals A1, A2 and A3

    GpioDataRegs.GPADAT.bit.GPIO10 = (Uint16)(A1);      //pin 61
    GpioDataRegs.GPADAT.bit.GPIO11 = (Uint16)(A2);      //pin 63
    GpioDataRegs.GPADAT.bit.GPIO12 = (Uint16)(A3);      //pin 58
    GpioDataRegs.GPADAT.bit.GPIO14 = (Uint16)(A*0.4);   //pin 62

   
    GpioDataRegs.GPADAT.bit.GPIO4 = (Uint16)(A*0.4);   //GPIO 4 is PWM 3



 EPwm3Regs.TBPRD = INV_PWM_TBPRD;                       // Set timer period
    EPwm3Regs.TBPHS.bit.TBPHS = 0x0000;           // Phase is 0
    EPwm3Regs.TBCTR = 0x0000;                     // Clear counter
    EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up-down
    EPwm3Regs.TBCTL.bit.PHSEN = TB_DISABLE;        // Disable phase loading
    EPwm3Regs.TBCTL.bit.SYNCOSEL = 1; // Sync Output Select: CTR = zero
    EPwm3Regs.rsvd2[0] = 0x0002; // EPWMxSYNCOUT Source Enable Register
    EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;       // Clock ratio to SYSCLKOUT
    EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;
//    EPwm3Regs.CMPA.bit.CMPA = (Uint16)(fDutyCycle * (float32)INV_PWM_HALF_TBPRD);
    EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;    // Load registers every ZERO
    EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
    EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
    EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR;            // Set PWM1A on Zero
    EPwm3Regs.AQCTLA.bit.CAD = AQ_SET;
    EPwm3Regs.AQCTLB.bit.CAU = AQ_SET;          // Set PWM1A on Zero
    EPwm3Regs.AQCTLB.bit.CAD = AQ_CLEAR;
    EPwm3Regs.AQSFRC.bit.RLDCSF = 3; // Load immediately
    EPwm3Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
    EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
    EPwm3Regs.DBCTL.bit.IN_MODE = DBA_ALL;
    EPwm3Regs.DBRED.bit.DBRED = EPwm1_DB;
    EPwm3Regs.DBFED.bit.DBFED = EPwm1_DB;