Part Number: TMS570LS3137
Hi,
I have been trying to transmit data within the RAM using mibspi1 configuring itself as both master and slave externally without using loopback.
I have got the following queries:
When internal loopback is enabled, the data is transmitted from TXRAM to RXRAM through mibspi1, the parity bits are getting stored at the location 0xFF0E0400 after it is calculated by the controller.
After the transfer of data, the parity bits in location 0xFF0E0600 are updated with what they are stored in 0xFF0E0400. Is it calculated by controller or is the data transmitted?
The same functionality is observed even if the loopback test mode is disabled.
And when the loopback test mode is disabled, the parity bits are to be sent along with the data. How can we know that the parity bits are sent as those can't be accessible by the CPU as mentioned?
And, how can the receiver know that the parity is enabled when the data is sent?
When the data is received, where are the parity bits stored?
Please answer my queries.
Thanks,
Susvitha.