Part Number: HD3SS3220
I have inherited a design from an engineer who has move onto better things.
His overall design and layout looks pretty good, but our client is having issues with throughput.
The basic concept is an interface board for a USB-C Camera. A body mounted camera connects to this board with a USB-C connector, then USB goes through a pair of HD3SS3220's and back out on another USB-C connctor. (It's all body-worn stuff, hence this intermediate interface board).
The issue is that in one cable orientation we can get 450 MB/s from the camera. In the other orientation the throughput drops to just 45 MB/s
I don't yet have permission to share the design files, but I can show this snapshot of the board layout:
My questions are:
1. The pairs in each lane are length and impedence matched. Should the separate lanes be length matched too? COuld this contribute to the throughput issues in various cable orientations?
2. The capacitors in each lane are 0.22uf, the datasheet reference design shows 0.1uf - could this have an impact? I don't have access to the design decisions as to how the capacitor values were chosen.
Any thoughts?