TDA4vM LPDDR4 Layout

1,Does TDA4vM LPDDR4 wiring need to consider packaging delay compensation?If necessary, can you provide the TDA4vM internal packaging delay table?
2,Can you provide IBIS model for TDA4vM?
3,Why does LPDDR4_CKE0 and LPDDR4_CA0 use different impedance in TDA4vM EVM LPDDR4 routing?
LPDDR4_CKE0(6mil-40ohm & 6mil-40ohm),LPDDR4_CA0(8mil-33ohm & 3mil-66ohm)