Part Number: AM4378
Dears,
When we use AM437x GPMC FPGA communication, we use the address/data line multiplexed, but the upper address line does not take effect (a[27:17]), the lower 16-bit address is correct, and the data can be read and written normally. For example, we writing a value of 0x2 to the fpga register address 0x1f3000, the results in the lower 16-bit address 0x3000 can be seen on the logic analyzer, followed by the data value 0x2. However, the upper address line[22:16] is always in the initial state 0, unchanged.
E.g write value 0x2 to register 0x1f3000 :
# echo 0x1f3000 0x2 > fpga_reg
HW connect:
gpmc_ad[15:0] mux as :gpmc_ad[15:0] , use as : fpga_ad[15:0]
gpmc_a[11:1] mux as gpmc_a[27:17] , use as : fpga_a[26:16]
We are using asynchronous mode:
the kernel source code :
dts configure:
pin mode：
mayi_fpga_default: mayi_fpga_default {
pinctrl-single,pins = <
0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ //gpmc_ad[15:0]-->gpmc_ad[15:0]--->fpga_ad[15:0];
0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
0x20 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad8.gpmc_ad8 */
0x24 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad9.gpmc_ad9 */
0x28 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad10.gpmc_ad10 */
0x2c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad11.gpmc_ad11 */
0x30 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad12.gpmc_ad12 */
0x34 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad13.gpmc_ad13 */
0x38 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad14.gpmc_ad14 */
0x3c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad15.gpmc_ad15 */
0x44 (PIN_OUTPUT | MUX_MODE4) /* gpmc_a1.gpmc_a17 */ // gpmc_a[11:1]-->gpmc_a[27:17]--->fpga_a[26:16];
0x48 (PIN_OUTPUT | MUX_MODE4) /* gpmc_a2.gpmc_a18 */
0x4c (PIN_OUTPUT | MUX_MODE4) /* gpmc_a3.gpmc_a19 */
0x50 (PIN_OUTPUT | MUX_MODE4) /* gpmc_a4.gpmc_a20 */
0x54 (PIN_OUTPUT | MUX_MODE4) /* gpmc_a5.gpmc_a21 */
0x58 (PIN_OUTPUT | MUX_MODE4) /* gpmc_a6.gpmc_a22 */
0x5c (PIN_OUTPUT | MUX_MODE4) /* gpmc_a7.gpmc_a23 */
0x60 (PIN_OUTPUT | MUX_MODE4) /* gpmc_a8.gpmc_a24 */
0x64 (PIN_OUTPUT | MUX_MODE4) /* gpmc_a9.gpmc_a25 */
0x68 (PIN_OUTPUT | MUX_MODE4) /* gpmc_a10.gpmc_a26 */
0x6c (PIN_OUTPUT | MUX_MODE4) /* gpmc_a11.gpmc_a27*/
0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
0x90 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
0x94 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
0x98 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_wen.gpmc_wen */
>;
};
timing setting as:
&gpmc {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&mayi_fpga_default>;
//pinctrl-1 = <&mayi_fpga_sleep>;
ranges = <0 0 0x08000000 0x04000000>; /* mayi fpga on CS0 space. Min partition = 64MB */
fpga@0,0 {
compatible = "mayi,gpmc-fpga";
reg = <0 0 0x04000000>;
bank-width = <2>;
gpmc,mux-add-data = <2>; //mux addr;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
//interrupt-parent = <&gpio0>;
//interrupts = <21 0x2>;
fpga-reset = <&gpio3 7 GPIO_ACTIVE_LOW>;
fpga-ready = <&gpio0 12 GPIO_ACTIVE_HIGH>; //input ,check high is ready ok;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <70>;
gpmc,cs-wr-off-ns = <60>;
gpmc,adv-on-ns = <0>;
gpmc,adv-rd-off-ns = <30>;
gpmc,adv-wr-off-ns = <30>;
gpmc,we-on-ns = <30>;
gpmc,we-off-ns = <60>;
gpmc,oe-on-ns = <30>;
gpmc,oe-off-ns = <70>;
gpmc,access-ns = <60>;
gpmc,rd-cycle-ns = <70>;
gpmc,wr-cycle-ns = <60>;
//gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <20>;
gpmc,cycle2cycle-samecsen = <10>;
gpmc,cycle2cycle-diffcsen = <0>;
gpmc,wr-access-ns = <60>; //?
gpmc,wr-data-mux-bus-ns = <30>;
#address-cells = <1>;
#size-cells = <1>;
};
};
The high-order address gpmc_a[11:1] is multiplexed into gpmc_a[27:17]. The pinmux configuration reads the value as follows, and the corresponding mode4 I think should be the corresponding address mode:
# devmem2 0x44e10844
/dev/mem opened.
Memory mapped at address 0xb6fe8000.
Value at address 0x44E10844 (0xb6fe8844): 0x10004
#
# devmem2 0x44e10848
/dev/mem opened.
Memory mapped at address 0xb6efd000.
Value at address 0x44E10848 (0xb6efd848): 0x10004
#
# devmem2 0x44e1084c
/dev/mem opened.
Memory mapped at address 0xb6f41000.
Value at address 0x44E1084C (0xb6f4184c): 0x10004
#
# devmem2 0x44e10850
/dev/mem opened.
Memory mapped at address 0xb6f94000.
Value at address 0x44E10850 (0xb6f94850): 0x10004
#
#
# devmem2 0x44e10854
/dev/mem opened.
Memory mapped at address 0xb6f5e000.
Value at address 0x44E10854 (0xb6f5e854): 0x10004
#
# devmem2 0x44e10858
/dev/mem opened.
Memory mapped at address 0xb6fc5000.
Value at address 0x44E10858 (0xb6fc5858): 0x10004
#
# devmem2 0x44e1085c
/dev/mem opened.
Memory mapped at address 0xb6f77000.
Value at address 0x44E1085C (0xb6f7785c): 0x10004
#
# devmem2 0x44e10860
/dev/mem opened.
Memory mapped at address 0xb6f93000.
Value at address 0x44E10860 (0xb6f93860): 0x10004
#
# devmem2 0x44e10864
/dev/mem opened.
Memory mapped at address 0xb6fa3000.
Value at address 0x44E10864 (0xb6fa3864): 0x10004
#
# devmem2 0x44e10868
/dev/mem opened.
Memory mapped at address 0xb6fd6000.
Value at address 0x44E10868 (0xb6fd6868): 0x10004
#
# devmem2 0x44e1086c
/dev/mem opened.
Memory mapped at address 0xb6f22000.
Value at address 0x44E1086C (0xb6f2286c): 0x10004
This problem is very urgent, trouble to help check where is abnormal, thank you so much! ! ! !