Part Number: ADS1258-EP
We're having trouble communicating with this device through the SPI port. We're using a Microsemi FPGA. We've tried a sample C program from the TI website. We are able to control the PWDN and RESET pins. START and CLKSEL are held high through hard wires. CS, SDI, SCLK and SDO connect to the FPGA SPI pins. The FPGA firmware has a Texas Instrument mode, which keeps the clock running continuously. This would seem to be necessary since the data sheet says "If SCLK is held inactive for 4096 or 256 fclk cycles, read or write operations in progress will terminate and the SPI interface resets."
There are other FPGA modes which do not do that. We have used a different mode successfully with a different TI A/D converter.
Questions:
1. Do we need to keep the SCLK line running in this manner with this device?
2. The sample code seems to read the data and status signals through the SPI in 8 bit chunks. Is that what we need to do?
3. Are there any samples of what the SPI signals would look like when successfully operating?
Below is a scope output showing an attempt at communication. You can see the clock is running continuously. The CS goes high at the start of communication. The SDI pin is toggled with the attempted command. However, the SDO pin seems to communicate almost randomly.