Part Number: LM98640QML-SP
Hello, I'm prototyping a CCD readout board (eventual custom design) using the LM98640CVAL. The reference level does come out each line (for a couple sample clocks duration) shortly after the LSYNC so we derived an external CLAMP signal to go high at that time (the level is outside the control range of the VCLP DAC so I couldn't set it manually). We get something that sorta works, though in feeding 4 video signals (two eval boards and using both converters) I see some significant differences in the A,B,C,D columns (especially between the two boards). I'm just a bit concerned that we don't have some register settings right (e.g., should the VCLP register 0x04 be a value of 0x00 or 0x40, or does that bit not matter?). Also, do we need to adjust the jumpers on the board (the VCLP pin connected to OS{1,2}+? I worry that is providing an undesired coupling between channels 1 and 2 or otherwise biasing the capture of the reference level. Do I expect to see large gain/offset differences between individual chips? Right now I have all the settings (PGA gains, etc.) common to all but am seeing differences in the "black level" of around 1000 counts. That seems huge. Any tips?