Part Number: PGA411-Q1
Hi team,
how to understanding the DEV_PHASE_CFG / EXTUVF_CFG register? if set EXTUVF_CFG to 0xb, My understanding is that if set 0x, it mean when the voltage is lower than UV1 or UV2, the OR inputs will have a high level; if set 10, it mean when the voltage is lower than UV1 and UV2 at the same time, the AND output pint will have a high level, does my understanding is right?
thank you